ZHCSD30 November   2014 CDCL1810A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Device Comparison Tables
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 DC Electrical Characteristics
    6. 8.6 AC Electrical Characteristics
    7. 8.7 AC Electrical Characteristics for the SDA/SCL Interface
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable/Disable
      2. 9.3.2 SDA/SCL Interface
        1. 9.3.2.1 SDA/SCL Bus Slave Device Address
        2. 9.3.2.2 SDA/SCL Connections Recommendations
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SDA/SCL Interface
      2. 9.5.2 Command Code Definition
      3. 9.5.3 SDA/SCL Timing Characteristics
      4. 9.5.4 SDA/SCL Programming Sequence
    6. 9.6 Register Maps
      1. 9.6.1 SDA/SCL Bus Configuration Command Bitmap
        1. 9.6.1.1 Byte 0:
        2. 9.6.1.2 Byte 1:
        3. 9.6.1.3 Byte 2:
        4. 9.6.1.4 Byte 3:
        5. 9.6.1.5 Byte 4:
        6. 9.6.1.6 Byte 5:
        7. 9.6.1.7 Byte 6:
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Distribution for Multiple TI Keystone DSPs
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 商标
    2. 13.2 静电放电警告
    3. 13.3 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

48-Pin
RGZ Package
(Top View)
pinout_CDCL1810A.gif
NOTE: Exposed thermal pad must be soldered to VSS.

The CDCL1810A is available in a 48-pin VQFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal pad serves both thermal and electrical grounding purposes.

NOTE

The device must be soldered to ground (VSS) using as many ground vias as possible. The device performance will be severely impacted if the exposed thermal pad is not grounded appropriately.

Pin Functions

PIN TYPE DESCRIPTION
NAME NUMBER
VDD 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41 Power 1.8V digital power supply.
AVDD 2, 5, 44, 47 Power 1.8V analog power supply.
VSS Exposed thermal pad and pin 12 Power Ground reference.
NC 1, 13, 45, 46, 48 I Not connected; leave open.
CLKP, CLKN 3, 4 I Differential LVDS input. Single-ended 1.8-V input can be dc-coupled to pin 3 with pin 4 either tied to pin 3 (recommended) or left open.
YP0, YN0
YP1, YN1
YP2, YN2
YP3, YN3
YP4, YN4
YP5, YN5
YP6, YN6
YP7, YN7
YP8, YN8
YP9, YN9		 6, 7
9, 10
15, 16
18, 19
21, 22
27, 28
30, 31
33, 34
40, 39
43, 42		 O 10 differential CML outputs.
SCL 24 I SCL serial clock pin. SCL tolerated 1.8V on the input only. Open drain. Always connect to a pull-up resistor.
SDA 25 I/O SDA bidirectional serial data pin. SDA tolerates 1.8V on the input only.Open drain. Always connect to a pull-up resistor.
ADD1, ADD0 37, 36 I Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed most significant bits (ADD[6:2]) of the 7-bit device address are 11010.
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