11.1 Layout Guidelines

Power consumption of the CDCLVP111 can be high enough to require attention to thermal management. For reliability and performance reasons, the die temperature must be limited to a maximum of 110°C. That is, as an estimate, ambient temperature (T_A) plus device power consumption times R_θJA must not exceed 110°C.

The device package has an exposed pad that provides the primary heat removal path to the printed-circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. Figure 18 shows a recommended land and via pattern.

11.2 Layout Example

Figure 18. Recommended PCB Layout

11.3 Thermal Considerations

The CDCLVD110A supports high temperatures on the printed-circuit board (PCB) measured at the thermal pad. The system designer must ensure that the maximum junction temperature is not exceeded. Ψ_JB can allow the system designer to measure the board temperature with a fine gauge thermocouple and back calculate the junction temperature using Equation 1. Note that Ψ_JB is close to R_θJB as 75% to 95% of a device's heat is dissipated by the PCB.

Further information can be found at Semiconductor and IC Package Thermal Metrics (SPRA953) and Using Thermal Calculation Tools for Analog Components (SLUA566).