8.1 Overview

The CDCLVD1204 LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing and termination are required to ensure correct operation of the device and to maximize signal integrity.

The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage different than the output common mode voltage of the CDCLVD1204, AC-coupling must be used. If the LVDS receiver has internal 100-Ω termination, external termination must be omitted.

8.2 Functional Block Diagram

8.3 Feature Description

The CDCLVD1204 is a low additive jitter LVDS fan-out buffer that can generate four copies of two selectable LVPECL, LVDS, or LVCMOS inputs. The CDCLVD1204 can accept reference clock frequencies up to 800 MHz while providing low output skew.

8.4 Device Functional Modes

The two inputs of the CDCLVD1204 are internally muxed together and can be selected through the control pin (see Table 1). Unused inputs and outputs can be left floating to reduce overall component cost. Both AC- and DC-coupling schemes can be used with the CDCLVD1204 to provide greater system flexibility.

8.4.1 LVDS Output Termination

Unused outputs can be left open without connecting any trace to the output pins.

The CDCLVD1204 can be connected to LVDS receiver inputs with DC- and AC-coupling as shown in Figure 10 and Figure 11 (respectively).

Figure 10. Output DC Termination

Figure 11. Output AC Termination (With the Receiver Internally Biased)

8.4.2 Input Termination

The CDCLVD1204 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.

LVDS drivers can be connected to CDCLVD1204 inputs with AC- and DC-coupling as shown in Figure 12 and Figure 13 (respectively).

Figure 12. LVDS Clock Driver Connected to CDCLVD1204 Input (AC-Coupled)

Figure 13. LVDS Clock Driver Connected to CDCLVD1204 Input (DC-Coupled)

Figure 14 shows how to connect LVPECL inputs to the CDCLVD1204. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 Vpp.

Figure 14. LVPECL Clock Driver Connected to CDCLVD1204 Input

Figure 15 illustrates how to couple a 2.5-V LVCMOS clock input to the CDCLVD1204 directly. The series resistance, R_S, must be placed close to the LVCMOS driver if required. 3.3-V LVCMOS clock input swing must be limited to V_IH ≤ V_CC.

Figure 15. 2.5-V LVCMOS Clock Driver Connected to CDCLVD1204 Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.