Figure 3. LVDS Output DC Configuration During Device Test
Figure 4. LVDS Output AC Configuration During Device Test
Figure 5. DC-Coupled LVCMOS Input During Device Test
Figure 6. Output Voltage and Rise/Fall Time
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B. Part to part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)