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SCAS884D August 2009 – December 2015 CDCLVP1102

PRODUCTION DATA.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage range⁽²⁾	–0.5	4.6	V
V_IN	Input voltage range ⁽³⁾	–0.5	V_CC + 0.5	V
V_OUT	Output voltage range ⁽³⁾	–0.5	V_CC + 0.5	V
I_IN	Input current		20	mA
I_OUT	Output current		50	mA
T_A	Specified free-air temperature (no airflow)	–40	85	°C
T_J	Maximum junction temperature		125	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All supply voltages must be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	2.375	2.50/3.30	3.60	V
T_A	Ambient temperature	–40		85	°C
T_PCB	PCB temperature (measured at thermal pad)			105	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾⁽³⁾			CDCLVP1102	UNIT
			RGT (VQFN)
			16 PINS
R_θJA	Junction-to-ambient thermal resistance	0 LFM⁽⁴⁾	51.8	°C/W
		150 LFM⁽⁴⁾	45
		400 LFM⁽⁴⁾	40.8
R_θJC(top)	Junction-to-case (top) thermal resistance		61.3	°C/W
R_θJB⁽⁵⁾	Junction-to-board thermal resistance		21.7	°C/W
ψ_JT	Junction-to-top characterization parameter		1.5	°C/W
ψ_JB	Junction-to-board characterization parameter		21.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		6.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).

(3) Connected to GND with four thermal vias (0.3-mm diameter).

(4) 2 x 2 vias on Pad

(5) θ_JP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN package.

6.5 Electrical Characteristics: LVCMOS Input

at V_CC = 2.375 V to 3.6 V and T_A = –40°C to 85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency				200	MHz
V_th	Input threshold voltage	External threshold voltage applied to complementary input	1.1		1.8	V
V_IH	Input high voltage		V_th + 0.1		V_CC	V
V_IL	Input low voltage		0		V_th – 0.1	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
ΔV/ΔT	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 3 and Figure 4 show DC test setup.

6.6 Electrical Characteristics: Differential Input

at V_CC = 2.375 V to 3.6 V and T_A = –40°C to 85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency	Clock input			2000	MHz
V_{IN, DIFF, PP}	Differential input peak-peak voltage	f_IN ≤ 1.5 GHz	0.1		1.5	V
V_{IN, DIFF, PP}	Differential input peak-peak voltage	1.5 GHz ≤ f_IN ≤ 2 GHz	0.2		1.5	V
V_ICM	Input common-mode level		1		V_CC – 0.3	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
ΔV/ΔT	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 5 and Figure 6 show DC test setup. Figure 7 shows AC test setup.

6.7 Electrical Characteristics: LVPECL Output

at V_CC = 2.375 V to 2.625 V and T_A = –40°C to 85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85ºC	V_CC – 1.26		V_CC – 0.9	V
V_OH	Output high voltage	T_PCB ≤ 105ºC	V_CC – 1.26		V_CC – 0.83	V
V_OL	Output low voltage	T_A ≤ 85ºC	V_CC – 1.7		V_CC – 1.3	V
V_OL	Output low voltage	T_PCB ≤ 105ºC	V_CC – 1.7		V_CC – 1.25	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.5		1.35	V
V_{AC_REF}	Input bias voltage⁽²⁾	I_{AC_REF} = 2 mA	V_CC – 1.6		V_CC – 1.1	V
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1 V			450	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3 V			450	ps
t_SK,PP	Part-to-part skew				100	ps
t_SK,O	Output skew				10	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz	–50		50	ps
		f_OUT = 100 MHz, V_IN,SE = V_CC, V_th = 1.25 V, 10 kHz to 20 MHz		0.089		ps, RMS
		f_OUT = 100 MHz, V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.093		ps, RMS
t_RJIT	Random additive jitter (with 50% duty cycle input)	f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.037		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.094		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.091		ps, RMS
t_R/t_F	Output rise/fall time	20% to 80%			200	ps
I_EE	Supply internal current	Outputs unterminated, T_A ≤ 85ºC			33	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB ≤ 105ºC			34	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2, T_A ≤ 85ºC			100	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2, T_PCB ≤ 105ºC			105	mA

(1) Figure 8 and Figure 9 show DC and AC test setup.

(2) Internally generated bias voltage (V_{AC_REF}) is for 3.3-V operation only. It is recommended to apply externally generated bias voltage for V_CC < 3.0 V.

6.8 Electrical Characteristics: LVPECL Output

at V_CC = 3.0 V to 3.6 V and T_A = –40°C to 85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85ºC	V_CC – 1.26		V_CC – 0.9	V
V_OH	Output high voltage	T_PCB ≤ 105ºC	V_CC – 1.26		V_CC – 0.85	V
V_OL	Output low voltage	T_A ≤ 85ºC	V_CC – 1.7		V_CC – 1.3	V
V_OL	Output low voltage	T_PCB ≤ 105ºC	V_CC – 1.7		V_CC – 1.3	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.65		1.35	V
V_{AC_REF}	Input bias voltage	I_{AC_REF} = 2 mA	V_CC – 1.6		V_CC – 1.1	V
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1 V			450	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3 V			450	ps
t_SK,PP	Part-to-part skew				100	ps
t_SK,O	Output skew				10	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz	–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input)	f_OUT = 100 MHz, V_IN,SE = V_CC, V_th = 1.65 V, 10 kHz to 20 MHz		0.081		ps, RMS
		f_OUT = 100 MHz, V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.097
		f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.050
		f_OUT = 100 MHz, V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.098
		f_OUT = 100 MHz, V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.095
t_R/t_F	Output rise/fall time	20% to 80%			200	ps
I_EE	Supply internal current	Outputs unterminated, T_A ≤ 85ºC			33	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB ≤ 105ºC			34	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2, T_A ≤ 85ºC			100	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2, T_PCB ≤ 105ºC			105	mA

(1) Figure 8 and Figure 9 show DC and AC test setup.

6.9 Typical Characteristics

at T_A = –40°C to 85°C (unless otherwise noted)

CDCLVP1102 tc_fqcy_diff_vout_swing01_cas884.gif

Figure 1. Differential Output Peak-To-Peak Voltage vs Frequency

CDCLVP1102 tc_fqcy_diff_vout_swing02_cas884.gif

Figure 2. Differential Output Peak-To-Peak Voltage vs Frequency