12.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains

Mixing Supplies: The CDCM6208V1F incorporates a very flexible power supply architecture. Each building block has its own power supply domain, and can be driven independently with 1.8 V, 2.5 V, or 3.3 V . This is especially of advantage to minimize total system cost by deploying multiple low-cost LDOs instead of one, more-expensive LDO. This also allows mixed IO supply voltages (e.g. one CMOS output with 1.8 V, another with 3.3 V) or interfacing to a SPI/I2C controller with 3.3 V supply while other blocks are driven from a lower supply voltage to minimize power consumption. The CDCM6208V1F current consumption is practically independent of the supply voltage, and therefore a lower supply voltage consumes lower device power. Also note that outputs Y3:0 if used for PECL swing will provide higher output swing if the according output domains are connected to 2.5 V or 3.3 V.

Power-on Reset: The CDCM6208V1F integrates a built-in POR circuit, that holds the device in powerdown until all input, digital, and PLL supplies have reached at least 1.06 V (min) to 1.24 V (max). After this power-on release, device internal counters start (see previous section on device power up timing) followed by device calibration. While the device digital circuit resets properly at this supply voltage level, the device is not ready to calibrate at such a low voltage. Therefore, for slow power up ramps, the counters expire before the supply voltage reaches the minimum voltage of 1.71 V. Hence for slow power-supply ramp rates, it is necessary to delay calibration further using the PDN input.

Slow power-up supply ramp: No particular power supply sequence is required for the CDCM6208V1F. However, it is necessary to ensure that device calibration occurs AFTER the DVDD supply as well as the VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC supply are all operational, and the voltage on each supply is higher than 1.45. This is best realized by delaying the PDN low-to-high transition. The PDN input incorporates a 50 kΩ resistor to DVDD. Assuming the DVDD supply ramp has a fixed time relationship to the slowest of all PLL and input power supplies, a capacitor from PDN to GND can delay the PDN input signal sufficiently to toggle PDN low-to-high AFTER all other supplies are stable. However, if the DVDD supply ramps much sooner than the PLL or input supplies, additional means are necessary to prevent PDN from toggling too early. A premature toggling of PDN would possibly result in failed PLL calibration, which can only be corrected by re-calibrating the PLL by either toggling PDN or RESET high-low-high.

Figure 57. PDN Delay When Using Slow Ramping Power Supplies (Supply Ramp > 50 ms)