11.2.1.1 Device Block-level Description

The CDCM6208V2G includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a universal input interface, a phase frequency detector (PFD), charge pump, partially integrated loop filter, and a feedback divider. Completing the CDCM6208V2G device are the combination of integer and fractional output dividers, and universal output buffers. The PLL is powered by on-chip low dropout (LDO), linear voltage regulators and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation of the PLL from any noise in the external power supply rail with a PSNR of better than -50 dB at all frequencies. The regulator capacitor pin REG_CAP should be connected to ground by a 10 µF capacitor with low ESR (e.g. below 1 Ω ESR) to ensure stability.

11.2.1.2 Device Configuration Control

Figure 39 illustrates the relationships between device states, the control pins, device initialization and configuration, and device operational modes. In pin mode, the state of the control pins determines the configuration of the device for all device states. In programming mode, the device registers are initialized to their default state and the host can update the configuration by writing to the device registers. A system may transition a device from pin mode to host connected mode by changing the state of the SI_MODE pins and then triggering a device reset (either via the RESETN pin or via setting the RESETN bit in the device registers). In reset, the device disables the outputs so that unwanted sporadic activity associated with device initialization does not appear on the device outputs.

11.2.1.3 Configuring the RESETN Pin

Figure 38 shows two typical applications examples of the RESETN pin.

Figure 38. RESETN/PWR Pin Configurations

Figure 38 (a) SPI / I2C mode only: shows the RESETN pin connected to a digital device that controls device reset. The resistor and capacitor combination ensure reset is held low even if the CDCM6208V2G is powered up before the host controller output signal is valid.

Figure 38 (b) SPI / I2C mode only:shows a configuration in which the user wishes to introduce a delay between the time that the system applies power to the device and the device exiting reset. If the user does not use a capacitor, then the device effectively ignores the state of the RESETN pin.

Figure 38 (c) Pin mode only: shows a configuration useful if the device is used in Pin Mode. Here device pin number 44 becomes the PWR input. An external pull down resistor can be used to pull this pin down. If the resistor is not installed, the pin is internally pulled high.

Figure 39 shows how the different possible device configurations and when the VCO becomes calibrated and the outputs turn on and off.

Figure 39. Device Power up and Configuration

11.2.1.4 Preventing False Output Frequencies in SPI/I2C Mode at Startup:

Some systems require a custom configuration and cannot tolerate any output to start up with a wrong frequency. Holding RESET low at power-up until the device is fully configured keeps all outputs disabled. The device calibrates automatically after RESET becomes released and starts out with the desired output frequency.

Figure 40. Reset Pin Control During Register Loading

11.2.1.5 Power Down

When the PDN pin = 0, the device enters a complete power down mode with a current consumption of no more than 1 mA from the entire device.

11.2.1.6 Device Power Up Timing:

Before the device outputs turn on after power up, the device goes through the following initialization routine:

Figure 41. Powerup Time

Figure 42. XTAL Startup Using NX3225GA 25 MHz (Step 2)

Figure 43. PLL Lock Behavior (Step 6)

11.2.1.7 Input Mux and Smart Input Mux

The Smart Input MUX supports auto-switching and manual-switching using control pin (and through register). The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes are suppressed at the MUX output.

Example 1:An application desired to auto-select the clock reference in SPI/I2C mode. During production testing however, the system needs to force the device to use the primary followed by the secondary input. The settings would be as follows:

1. Tie REF_SEL pin always high
2. For primary clock input testing, use R4[13:12] = 10
3. For secondary clock input testing, set R4[13:12] = 11.
4. For the auto-mux setting in the final product shipment, set R3[13:12]=01 or 00

Example 2: The application wants to select the clock input manually without programming SPI/I2C. In this case, program R4[13:12] = 11, and select primary or secondary input by toggling REF_SEL low or high.

SmartMux input frequency limitation: In the automatic mode, the frequencies of both inputs to the smart mux (PRI_REF divided by R and SEC_REF) need to be similar; however, they can vary by up to 20%.

Switching behavior: The input clocks can have any phase. When switching happens between one input clock to the other, the phase of the output clock slowly transitions to the phase of the newly selected input clock. There will be no-phase jump at the output. The phase transition time to the new reference clock signal depends on the PLL loop filter bandwidth. Auto-switch assigns higher priority to PRI_REF and lower priority to SEC_REF. The timing diagram of an auto-switch at the input MUX is shown in Figure 44.

Figure 44. Smart Input MUX Auto-Switch Mode Timing Diagram

11.2.1.8 Universal INPUT Buffer (PRI_REF, SEC_REF)

The universal input buffers support multiple signaling formats (LVDS, CML or LVCMOS) and these require external termination schemes. The secondary input buffer also supports crystal inputs and Table 28 provides the characteristics of the crystal that can be used. Both inputs incorporate hysteresis.

11.2.1.9 VCO Calibration

The LC VCO is designed using high-Q monolithic inductors and has low phase noise characteristics. The VCO of the CDCM6208V2G must be calibrated to ensure that the clock outputs deliver optimal phase noise performance. Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO. While transparent to the user, the CDCM6208V2G and the host system perform the following steps comprising a VCO calibration sequence:

1. Normal Operation- When the CDCM6208V2G is in normal (operational) mode, the state of both the power down pin (PDN) and reset pin (RESETN) is high.
2. Entering the reset state – If the user wishes to restore all device defaults and initiate a VCO calibration sequence, then the host system must place the device in reset via the PDN pin, via the RESETN pin, or by removing and restoring device power. Pulling either of these pins low places the device in the reset state. Holding either pin low holds the device in reset.
3. Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through the device reset command initiated via the host interface. Exiting the reset state occurs automatically after power is applied and/or the system restores the state of the PDN or RESETN pins from the low to high state. Exiting the reset state using this method causes the device defaults to be loaded/reloaded into the device register bank. Invoking a device reset via the register bit does not restore device defaults; rather, the device retains settings related to the current clock frequency plan. Using this method allows for a VCO calibration for a frequency plan other than the default state (i.e. the device calibrates the VCO based on the settings contained within the register bank at the time that the register bit is accessed). The nominal state of this bit is low. Writing this bit to a high state and then returning it to the low state invokes a device reset without restoring device defaults.
4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase locked loops have stabilized prior to calibrating the VCO.
5. VCO Calibration – The CDCM6208V2G calibrates the VCO. During the calibration routine, the device holds all outputs in reset so that the CDCM6208V2G generates no spurious clock signals.

11.2.1.10 Reference Divider (R)

The reference (R) divider is a continuous 4-b counter (1 – 16) that is present on the primary input before the Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the R divider sets the input frequency for the Smart MUX, and the auto switch capability of the Smart MUX can then be employed as long as the secondary input frequency is no more than ± 20% different from the output of the R divider.

11.2.1.11 Input Divider (M)

The input (M) divider is a continuous 14-b counter (1 – 16384) that is present after the Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the M divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to 100 MHz.

11.2.1.12 Feedback Divider (N)

The feedback (N) divider is made up of cascaded 8-b counter divider (1 – 256) followed by a 10-b counter divider (1 – 1024) that are present on the feedback path of the PLL. It is operational in the frequency range of 8 kHz to 800 MHz. The output of the N divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to 100 MHz. The frequency out of the first divider is required to be less than or equal to 200 MHz to ensure proper operation.

11.2.1.13 Prescaler Dividers (PS_A, PS_B)

The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers (PS_A to the dividers for Outputs 0, 1, 4, and 5 and PS_B to the dividers for Outputs 2, 3, 6, and 7. PS_A also completes the PLL as it also drives the input of the Feedback Divider (N).

11.2.1.14 Phase Frequency Detector (PFD)

The PFD takes inputs from the Smart Input MUX output and the feedback divider output and produces an output that is dependent on the phase and frequency difference between the two inputs. The allowable range of frequencies at the inputs of the PFD is from 8 kHz to 100 MHz.

11.2.1.15 Charge Pump (CP)

The charge pump is controlled by the PFD which dictates either to pump up or down in order to charge or discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then converted to a voltage that drives the control voltage node of the internal VCO through the loop filter. The range of the charge pump current is from 500 µA to 4 mA.

11.2.1.16 Programmable Loop Filter

The on-chip PLL supports a partially internal and partially external loop filter configuration for all PLL loop bandwidths where the passive external components C1, C2, and R2 are connected to the ELF pin as shown in Figure 45 to achieve PLL loop bandwidths from 400 kHz down to 10 Hz.

Figure 45. CDCM6208V2G PLL Loop Filter Topology

11.2.1.16.4 Fractional Output Divider (FOD)

The CDCM6208V2G incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non-integer output divide ratios of the PLL frequencies. This feature is useful when systems require different, unrelated frequencies. The fractional output divider architecture is shown in Figure 46.

Figure 46. Fractional Output Divider Principle Architecture
(Simplified Graphic, not Showing Output Divider Bypass Options)

The fractional output divider requires an input frequency between 400 MHz and 800 MHz, and outputs any frequency equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider block has a first stage integer pre-divider followed by a fractional sigma-delta output divider block that is deep enough such as to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency in the range of 400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The fractional values available are all possible 20-b representations of fractions within the following range:

• 1.0 ≤ ƒrac_DIV ≤ 1.9375
• 2.0 ≤ ƒrac_DIV ≤ 3.875
• 4.0 ≤ ƒrac_DIV ≤ 5.875
• x.0 ≤ ƒrac_DIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254
• 254.0 ≤ ƒrac_DIV ≤ 255.875
• 256.0 ≤ ƒrac_DIV ≤ 256.99999

The CDCM6208V2G user GUI comprehends the fractional divider limitations; therefore, using the GUI to comprehend frequency planning is recommended.

The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from 50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths (approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (< 1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional divider enable bit, which engages the higher performing integer divider.

11.2.1.16.5 Output Synchronization

Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208V2G, this signal comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output synchronization is to toggle the SYNCN pin. When SYNC is asserted (V_SYNCN ≤ V_IL), all outputs are disabled (high-impedance) and the output dividers are reset. When SYNC is de-asserted (V_SYNCN ≥ V_IH), the device first internally latches the signal, then retimes the signal with the pre-scaler, and finally turns all outputs on simultaneously. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles. For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle.

The SYNC feature is particularly helpful in systems with multiple CDCM6208V2G. If SYNC is released simultaneously for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices configured to identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew uncertainty due to sync remains ±2 clock cycles.

Outputs Y0, Y1, Y4, and Y5 are aligned with the PS_A output while outputs Y2, Y3, Y6, and Y7 are aligned with the PS_B output). All outputs Y[7:0] turn on simultaneously, if PS_B and PS_A are set to identical divide values (PS_A=PS_B).

Figure 47. SYNCN to Output Delay Uncertainty

11.2.1.16.7 Staggered CLK Output Powerup for Power Sequencing of a DSP

DSPs are sensitive to any kind of voltage swing on unpowered input rails. To protect the DSP from long-term reliability problems, it is recommended to avoid any clock signal to the DSP until the DSP power rail is also powered up. This can be achieved in two ways using the CDCM6208V2G:

1. Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on outputs one by one through serial interface after each DSP rail becomes powered up accordingly.
2. Output Power supply domain control: An even easier scheme might be to connect the clock output power supply VDD_Yx to the corresponding DSP input clock supply domain. In this case, the CDCM6208V2G output will remain disabled until the DSP rails ramps up as well. Figure 48 shows the turn-on behavior.

Figure 48. Sequencing the Output Turn-on Through Sequencing the Output Supplies. Output Y2 Powers Up While Output Y0 is Already Running.

11.2.2.1 Jitter Considerations in SERDES Systems

The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using Serializer and De-serializer implementation (for example, 10 GigEthernet). Fully estimating the clock jitter impact on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR bandwidth. As can be seen in Figure 49, the bandwidth of TX and RX is the frequency range in which clock jitter adds without any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate clock jitter with a 20 dB/dec or even steeper roll-off.

Figure 49. Serial Link Jitter Budget Explanation

Example: SERDES link with KeyStone™ I DSP

The SERDES TX PLL of the TI KeyStone™ I DSP family (see SPRABI2) for the SRIO interface, has a 13 MHz PLL bandwidth (Low Pass Characteristic, see Figure 49). The CDCM6208V2, pin-mode 27, was characterized in this example over Process, Voltage and Temperature (PVT) with a low pass filter of 13 MHz to simulate the TX PLL. The attenuation is higher or equal to 20 dB/dec; therefore, the characterization used 20 dB/dec as worst case.

Table 37 shows the maximum Total Jitter⁽¹⁾ over PVT with and without Low Pass Filter.

Figure 50 shows the maximum Total Jitter with, without Low Pass Filter characteristic and the maximum TI KeyStone™ I specification.

Figure 50. Maximum Jitter Over PVT

11.2.2.2 Jitter Considerations in ADC and DAC Systems

A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity. The following test results were achieved connecting the CDCM6208V2G to ADC and DACs:

Figure 51. IF = 60 MHz Fclk = 122.88 MHz Baseline (Lab Clk Generator) ADC: ADS62P48-49

Figure 52. IF = 60 MHz Fclk = 122.88 MHz CDCM6208V2G driving ADC

Observation: up to an IF = 100 MHz, The ADC performance when driven by the CDCM6208V2G (Figure 52) is similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering (Figure 51).

Conclusion Therefore, the CDCM6208V2G is usable for applications up to 100 MHz IF. For IF above 100 MHz, the SNR starts degrading in our experiments. Measurements were conducted with ADC connected to Y0 and other outputs running at different integer frequencies.

Important note on crosstalk: it is highly recommended that both pre-dividers are configured identically, as otherwise SFDR and SNR suffer due to crosstalk between the two pre-divider frequencies.

Figure 53. DAC Driven by Lab Source and CDCM6208V2G in Comparison (Performance Identical)

Observation/Conclusion: The DAC performance was not degraded at all by the CDCM6208V2G compared to driving the DAC with a perfect lab source. Therefore, the CDCM6208V2G provides sufficient low noise to drive a 245.76 MHz DAC.

11.2.3.1 Typical Device Jitter

Figure 54. Typical Device Output Phase Noise and Jitter for 25 MHz

Figure 55. Typical Device Output Phase Noise and Jitter for 312.5 MHz

Figure 56. Phase Noise Plot for Jitter Cleaning Mode (blue) and Synthesizer Mode (green)