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ZHCSF03 March 2016 CDCM6208V2G

PRODUCTION DATA.

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8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER	MIN	MAX	UNIT
Supply Voltage Range, VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD	-0.5	4.6	V
Input Voltage Range CMOS control inputs, V_IN	-0.5	4.6 and V _DVDD+ 0.5	V
Input Voltage Range PRI/SEC inputs		4.6 and V_VDDPRI.SEC+ 0.5	V
Output Voltage Range, V_OUT	-0.5	V_YxYy+ 0.5	V
Input Current, I_IN		20	mA
Output Current, I_OUT		50	mA
Junction Temperature, T_J		125	°C
Storage temperature range, T_stg	-65	150	°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute—maximum—rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
VDD_Yx_Yy	Output Supply Voltage		1.71	1.8/2.5/3.3	3.465	V
VDD_PLL1 VDD_PLL2	Core Analog Supply Voltage		1.71	1.8/2.5/3.3	3.465	V
DVDD	Core Digital Supply Voltage		1.71	1.8/2.5/3.3	3.465	V
VDD_PRI, VDD_SEC	Reference Input Supply Voltage		1.71	1.8/2.5/3.3	3.465	V
ΔVDD/Δt	VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight together PDN low-high is delayed ⁽¹⁾				50 < t_PDN	ms
T_A	Ambient Temperature		-40		85	°C
SDA and SCL in I ² C MODE (SI_MODE[1:0] = 01)
V_I	Input Voltage	DVDD = 1.8 V	–0.5		2.45	V
V_I	Input Voltage	DVDD = 3.3 V	–0.5		3.965	V
d_R	Data Rate			100 400		kbps
V_IH	High-level input voltage		0.7 x DVDD			V
V_IL	Low-level input voltage				0.3 x DVDD	V
C_{BUS_I2C}	Total capacitive load for each bus line				400	pF

(1) For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating. For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD, VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly Figure 57 for details.

8.4 Thermal Information, Airflow = 0 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

THERMAL METRIC⁽¹⁾		CDCM6208	UNIT
		RGZ
		48 PINS VQFN
R_θJA	Junction-to-ambient thermal resistance	30.27	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	16.58
R_θJB	Junction-to-board thermal resistance	6.83
ψ_JT	Junction-to-top characterization parameter	0.23
ψ_JB	Junction-to-board characterization parameter	6.8
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.06

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(3) Connected to GND with 36 thermal vias (0.3 mm diameter).

(4) θ_JB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.5 Thermal Information, Airflow = 150 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

THERMAL METRIC⁽¹⁾		CDCM6208	UNIT
		RGZ
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	21.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance
R_θJB	Junction-to-board thermal resistance	6.61
ψ_JT	Junction-to-top characterization parameter	0.37
ψ_JB	Junction-to-board characterization parameter
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.06

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(3) Connected to GND with 36 thermal vias (0.3 mm diameter).

(4) θ_JB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.6 Thermal Information, Airflow = 250 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

THERMAL METRIC⁽¹⁾		CDCM6208	UNIT
		RGZ
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	19.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance
R_θJB	Junction-to-board thermal resistance	6.6
ψ_JT	Junction-to-top characterization parameter	0.45
ψ_JB	Junction-to-board characterization parameter
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.06

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(3) Connected to GND with 36 thermal vias (0.3 mm diameter).

(4) θ_JB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.7 Thermal Information, Airflow = 500 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

THERMAL METRIC⁽¹⁾		CDCM6208	UNIT
		RGZ
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	17.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance
R_θJB	Junction-to-board thermal resistance	6.58
ψ_JT	Junction-to-top characterization parameter	0.58
ψ_JB	Junction-to-board characterization parameter
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.05

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(3) Connected to GND with 36 thermal vias (0.3 mm diameter).

(4) θ_JB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.8 Single Ended Input Characteristics

(SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL), DVDD = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, T_A = –40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Voltage		0.8 x DVDD			V
V_IL	Input Low Voltage				0.2 x DVDD	V
I_IH	Input High Current	DVDD = 3.465V, V_IH = 3.465 V (pull-up resistor excluded)			30	µA
I_IL	Input Low Current	DVDD = 3.465V, V_IL= 0 V			-30	µA
ΔV/ΔT	PDN, RESETN, SYNCN, REF_SEL Input Edge Rate	20% - 80%	0.75			V/ns
minPulse	PDN, RESETN, SYNCN low pulse to trigger proper device reset		10			ns
C _IN	Input Capacitance			2.25		pF
RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]:
R	Input Pullup and Pulldown Resistor		35	50	65	kΩ
SDA and SCL in I ² C Mode (SI_MODE[1:0]=01)
V_{HYS_I2C}	Input hysteresis	DVDD = 1.8 V	0.1 V_DVDD			V
V_{HYS_I2C}	Input hysteresis	DVDD = 2.5/3.3 V	0.05 V_DVDD			V
I_H	High-level input current	V_I = DVDD	–5		5	µA
V_OL	Output Low Voltage	I_OL= 3mA			0.2 x DVDD	V
C_IN	Input Capacitance terminal				5	pF

8.9 Single Ended Input Characteristics (PRI_REF, SEC_REF)

VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T_A = –40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Reference and Bypass Input Frequency	VDD_PRI/SEC = 1.8 V	0.008		200	MHz
f_IN	Reference and Bypass Input Frequency	VDD_PRI/SEC = 3.3 V	0.008		250	MHz
V_IH	Input High Voltage		0.8 x VDD_PRI/VDD_SEC			V
V_IL	Input Low Voltage				0.2 x VDD_PRI/VDD_SEC	V
V_HYST	Input hysteresis		20	65	150	mV
I_IH	Input High Current	VDD_PRI/VDD_SEC = 3.465 V, V_IH = 3.465 V			30	µA
I_IL	Input Low Current	VDD_PRI/VDD_SEC = 3.465 V, V_IL = 0 V			-30	µA
ΔV/ΔT	Reference Input Edge Rate	20% - 80%	0.75			V/ns
IDC _SE	Reference Input Duty Cycle	f _PRI ≤ 200MHz	40%		60%
IDC _SE	Reference Input Duty Cycle	200 ≤ f_PRI ≤ 250 MHz	43%		60%
C_IN	Input Capacitance			2.25		pF

8.10 Differential Input Characteristics (PRI_REF, SEC_REF)

VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T_A = –40°C TO 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Reference and Bypass Input Frequency		0.008		250	MHz
V_I	Differential Input Voltage Swing, Peak-to-Peak	VDD_PRI/SEC = 2.5/3.3 V	0.2		1.6	V_PP
V_I	Differential Input Voltage Swing, Peak-to-Peak	VDD_PRI/SEC = 1.8 V	0.2		1	V_PP
V_ICM	Input Common Mode Voltage	CML input signaling, R4[7:6] = 00	VDD_PRI/VDD_SEC-0.4		VDD_PRI/VDD_SEC-0.1	V
V_ICM	Input Common Mode Voltage	LVDS, VDD_PRI/SEC = 1.8/2.5/3.3 V, R4[7:6] = 01, R4.1 = d.c., R4.0 = d.c.	0.8	1.2	1.5	V
V_HYST	Input hysteresis	LVDS (Q4[7:6,4:3] = 01)	15		65	mV_pp
V_HYST	Input hysteresis	CML (Q4[7:6,4:3] = 00)	20		85	mV_pp
I_IH	Input High Current	VDD_PRI/SEC = 3.465 V, V_IH = 3.465 V			30	µA
I_IL	Input Low Current	VDD_PRI/SEC = 3.465V, V_IL = 0 V			-30	µA
ΔV/ΔT	Reference Input Edge Rate	20% - 80%	0.75			V/ns
IDC_DIFF	Reference Input Duty Cycle		30%		70%
C_IN	Input Capacitance			2.7		pF

8.11 Crystal Input Characteristics (SEC_REF)

VDD_SEC = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V,T_A = –40°C to 85°C

PARAMETER		MIN	TYP	MAX	UNIT
MODE OF OSCILLATION		FUNDAMENTAL
Frequency	See note ⁽¹⁾	10		30.72	MHz
Frequency	See note ⁽²⁾	30.73		50	MHz
Equivalent Series Resistance (ESR)	10 MHz			150⁽⁴⁾	Ω
	25 MHz			70⁽⁵⁾
	50 MHz			30⁽⁶⁾
On-chip load capacitance	1.8 V / 3.3 V SEC_REFP	3.5	4.5	5.5	pF
	1.8 V SEC_REFN	5.5	7.25	8.5
	3.3 V SEC_REFN	6.5	7.34	8.5
Drive Level	See note ⁽³⁾			200	µW

(1) Verified with crystals specified for a load capacitance of CL=8pF, the pcb related capacitive load was estimated to be 2.3pF, and completed with a load capacitors of 4pF on each crystal terminal connected to GND. XTALs tested: NX3225GA 10MHz EXS00A-CG02813 CRG, NX3225GA 19.44MHz EXS00A-CG02810 CRG, NX3225GA 25MHz EXS00A-CG02811 CRG, and NX3225GA 30.72MHz EXS00A-CG02812 CRG.

(2) For 30.73 MHz to 50 MHz, it is recommended to verify sufficient negative resistance and initial frequency accuracy with the crystal vendor. The 50 MHz use case was verified with a NX3225GA 50MHz EXS00A-CG02814 CRG. To meet a minimum frequency error, the best choice of the XTAL was one with C_L = 7pF instead of C_L = 8pF.

(3) Maximum drive level measured was 145 µW; XTAL should at least tolerate 200 µW

(4) With NX3225GA_10M the measured remaining negative resistance on the EVM is 6430 Ω (43 x margin)

(5) With NX3225GA_25M the measured remaining negative resistance on the EVM is 1740 Ω (25 x margin)

(6) With NX3225GA_50M the measured remaining negative resistance on the EVM is 350 Ω (11 x margin)

8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V; T_A = –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	Output High Voltage	Status 1, Status 0, and SDO only; SDA is open drain and relies on external pullup for high output; I_OH = 1 mA	0.8 x DVDD			V
V_OL	Output Low Voltage	I_OL = 1 mA			0.2 x DVDD	V
V_slew	Output slew rate	30% - 70%	0.5			V/ns
I_OZH	3-stat Output High Current	DVDD = 3.465 V, V_IH = 3.465 V			5	µA
I_OZL	3-stat Output Low Current	DVDD = 3.465 V, V_IL = 0 V			-5	µA
t_LOS	Status Loss of Signal Detection Time	LOS_REFfvco		1	2	1/f _PFD
t_LOCK	Status PLL Lock Detection Time	Detect lock		2304		1/f _PFD
t_LOCK	Status PLL Lock Detection Time	Detect unlock		512		1/f _PFD

8.13 PLL Characteristics

VDD_PLLx, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T_A = –40°C TO 85°C

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_VCO	VCO Frequency Range		2.39		2.55	GHz
K_VCO	VCO Gain	2.39 GHz		178		MHz/V
		2.50 GHz		204
		2.55 GHz		213
f_PFD	PFD Input Frequency		0.008		100	MHz
I_CP-L	High Impedance Mode Charge Pump Leakage			±700		nA
f_FOM	Estimated PLL Figure of Merit (FOM)	Measured in-band phase noise at the VCO output minus 20log(N-divider) at the flat region		–224		dBc/Hz
t_STARTUP	Startup time (see Figure 41 )	Power supply ramp time of 1ms from 0 V to 1.7 V, final frequency accuracy of 10 ppm, f_PFD = 25 MHz, C_{PDN_to_GND} = 22nF
		w/ PRI input signal		12.8		ms
		w/ NDK 25 MHz crystal		12.85		ms

8.14 LVCMOS Output Characteristics

VDD_Yx_Yy = 1.71 V to 1.89V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T_A = –40°C TO 85°C

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT-F	Output Frequency	Fract Out divVDD_Yx_Yy = 2.5/3.3 V	0.78		250	MHz
		Integer out divVDD_Yx_Yy = 2.5/3.3 V	1.55		250
		Int or frac out divVDD_Yx_Yy = 1.8 V	0.78/1.5		200
f_ACC-F	Output Frequency Error ⁽¹⁾	Fractional Output Divider	–1		1	ppm
V_OH	Output High Voltage (normal mode)	VDD_Yx = min to max, I_OH = -1 mA	0.8 x VDD_Yx_Yy			V
V_OL	Output Low Voltage(normal mode)	VDD_Yx = min to max, I_OL = 100 µA			0.2 x VDD_Yx_Yy	V
V_OH	Output High Voltage (slow mode)	VDD_Yx = min to max, I_OH = -100 µA	0.7 x VDD_Yx_Yy			V
V_OL	Output Low Voltage(slow mode)	VDD_Yx = min to max, I_OL = 100 µA			0.3 x VDD_Yx_Yy	V
I_OH	Output High Current	V _OUT = VDD_Yx_Yy/2
		Normal mode	–50		-8	mA
		Slow mode	–45		-5	mA
I_OL	Output Low Current	V _OUT = VDD_Yx_Yy/2
		Normal mode	10		55	mA
		Slow mode	5		40	mA
t_SLEW-RATE-N	Output Rise/Fall Slew Rate (normal mode)	20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, C_L = 5 pF		5.37		V/ns
t_SLEW-RATE-N	Output Rise/Fall Slew Rate (normal mode)	20% to 80%, VDD_Yx_Yy = 1.8 V, C_L = 5 pF		2.62		V/ns
t_SLEW-RATE-S	Output Rise/Fall Slew Rate (slow mode)	20% to 80%, VDD_Yx_Yy = 2.5/3.3 V, C_L = 5 pF		4.17		V/ns
t_SLEW-RATE-S	Output Rise/Fall Slew Rate (slow mode)	20% to 80%, VDD_Yx_Yy = 1.8 V, C_L = 5 pF		1.46		V/ns
PN-floor	Phase Noise Floor	f_OUT = 122.88 MHz		–159.5	–154	dBc/Hz
ODC	Output Duty Cycle	Not in bypass mode	45%		55%
R_OUT	Output Impedance	V _OUT = VDD_Yx/2
R_OUT	Output Impedance	Normal mode Slow mode	30 45	50 74	90 130	Ω

(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of a multiple 1 over 2²⁰, the actual output frequency error is 0.
Note: In LVCMOS Mode, positive and negative outputs are in phase.

8.15 LVPECL (High-Swing CML) Output Characteristics

VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, T_A = –40°C TO 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT-I	Output frequency	Integer Output Divider	1.55		800	MHz
V_CM-DC	Output DC coupled common mode voltage	DC coupled with 50 Ω external termination to VDD_Yx_Yy		VDD_Yx_ Yy – 0.4		V
\|V_OD\|	Differential output voltage	100 Ω diff load AC coupling (See Figure 11), f_OUT ≤ 250 MHz
		VDD_Yx_Yy ≤ 1.89 V	0.45	0.75	1.12	V
		VDD_Yx_Yy ≥ 2.375 V	0.6	0.8	1.12	V
		100 Ω diff load AC coupling (See Figure 11), f_OUT ≥ 250 MHz
		VDD_Yx_Yy ≤ 1.89 V		0.73		V
		VDD_Yx_Yy ≥ 2.375 V	0.55	0.75	1.12	V
V_OUT	Differential output peak-to-peak voltage			2 x \|V_OD\|		V
t_R/t_F	Output rise/fall time	±200 mV around crossing point	109		217	ps
t_R/t_F	Output rise/fall time	20% to 80% V_OD		211		ps
t_slew	Output rise/fall slew rate		3.7	5.1	7.3	V/ns
PN-floor	Phase noise floor	VDD_Yx_Yy = 3.3 V (See Figure 53)		–161.4	–155.8	dBc/Hz
ODC	Output duty cycle	Not in bypass mode	47.5%		52.5%
R_OUT	Output impedance	measured from pin to VDD_Yx_Yy		50		Ω

8.16 CML Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, T_A = –40°C to 85°C

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
f_OUT-I	Output frequency	Integer Output Divider		1.55		800	MHz
V_CM-AC	Output AC coupled common mode voltage	AC coupled with 50 Ω receiver termination			VDD_Yx_Yy – 0.46		V
V_CM-DC	Output DC coupled common mode voltage	DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy			VDD_Yx_Yy – 0.2		V
\|V_OD\|	Differential output voltage	100 Ω diff load AC coupling, (See Figure 11)		0.3	0.45	0.58	V
V_OUT	Differential output peak-to-peak voltage				2 x \|V_OD\|		V
t_R/t_F	Output rise/fall time	20% to 80%	VDDYx = 1.8 V	100	151	300	ps
t_R/t_F	Output rise/fall time	20% to 80%	VDDYx = 2.5 V/3.3 V	100	143	200	ps
PN-floor	Phase noise floor at > 5 Hz offset	f_OUT = 122.88 MHz	VDD_Yx_Yy = 1.8 V		–161.2	–155.8	dBc/Hz
PN-floor	Phase noise floor at > 5 Hz offset	f_OUT = 122.88 MHz	VDD_Yx_Yy = 3.3 V		–161.2	–153.8	dBc/Hz
ODC	Output duty cycle	Not in bypass mode		47.5%		52.5%
R_OUT	Output impedance	measured from pin to VDD_Yx_Yy			50		Ω

8.17 LVDS (Low-Power CML) Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465V, T_A = –40°C to 85°C

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
f_OUT-I	Output frequency	Integer output divider		1.55		400	MHz
f_OUT-F	Output frequency	Fractional output divider		0.78		400	MHz
f_ACC-F	Output frequency error ⁽¹⁾	Fractional output divider		-1		1	ppm
V_CM-AC	Output AC coupled common mode voltage	AC coupled with 50 Ω receiver termination			VDD_Yx_Yy – 0.76		V
V_CM-DC	Output DC coupled common mode voltage	DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy			VDD_Yx_Yy – 0.13		V
\|V_OD\|	Differential output voltage	100 Ω diff load AC coupling, (See Figure 11)		0.247	0.34	0.454	V
V_OUT	Differential output peak-to-peak voltage				2 x \|V_OD\|		V
t_R/t_F	Output rise/fall time	±100mV around crossing point				300	ps
PN-floor	Phase noise floor	f_OUT= 122.88 MHz	VDD_Yx = 1.8 V		–159.3	–154.5	dBc/Hz
PN-floor	Phase noise floor	f_OUT= 122.88 MHz	VDD_Yx = 2.5/3.3 V		–159.1	–154.9	dBc/Hz
ODC	Output duty cycle	Not in bypass mode	Y[3:0]	47.5%		52.5%
ODC	Output duty cycle	Not in bypass mode	Y[7:4]	45%		55%
R_OUT	Output impedance	Measured from pin to VDD_Yx_Yy			167		Ω

(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of a multiple of 1 over 2²⁰, the actual output frequency error is 0.

8.18 HCSL Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V, T_A = –40°C to 85°C

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
f_OUT-I	Output frequency	Integer Output Divider		1.55		400	MHz
f_OUT-F	Output frequency	Fractional Output Divider		0.78		400	MHz
f_ACC-F	Output Frequency Error ⁽¹⁾	Fractional Output Divider		-1		1	ppm
V_CM	Output Common Mode Voltage	VDD_Yx_Yy = 2.5/3.3 V		0.2	0.34	0.55	V
V_CM	Output Common Mode Voltage	VDD_Yx_Yy = 1.8 V		0.2	0.33	0.55	V
\|V_OD\|	Differential Output Voltage	VDD_Yx_Yy = 2.5/3.3 V		0.4	0.67	1.0	V
\|V_OD\|	Differential Output Voltage	VDD_Yx_Yy = 1.8 V		0.4	0.65	1.0	V
V_OUT	Differential Output Peak-to-peak Voltage	VDD_Yx_Yy = 2.5/3.3 V		1.0		2.1	V
V_OUT	Differential Output Peak-to-peak Voltage	VDD_Yx_Yy = 1.8 V			2 x\|V_OD\|		V
t_R/t_F	Output Rise/Fall Time	Measured from V_DIFF= –100 mV to V_DIFF = +100mV, VDD_Yx_Yy = 2.5/3.3 V		100	167	250	ps
t_R/t_F	Output Rise/Fall Time	Measured from V_DIFF= –100 mV to V_DIFF= +100 mV, VDD_Yx_Yy = 1.8 V		120	192	295	ps
PN-floor	Phase Noise Floor	f_OUT = 122.88 MHz	VDD_Yx_Yy = 1.8 V		–158.8	–153	dBc/Hz
PN-floor	Phase Noise Floor	f_OUT = 122.88 MHz	VDD_Yx = 2.5/3.3 V		–157.6	–153	dBc/Hz
ODC	Output Duty Cycle	Not in bypass mode		45%		55%

(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of A 1/2²⁰ multiple, the actual output frequency error is 0.

8.19 Output Skew and Sync to Output Propagation Delay Characteristics

VDD_Yx_Yy = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, T_A = –40°C to 85°C

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_PD-PS	Propagation delay SYNCN↑ to output toggling high	f _VCO= 2.5 GHz	PS_A = 4	9	10.5	11	1/f_{PS_A}
			PS_A = 5	9	10.2	11	1/f_{PS_A}
			PS_A = 6	9	10.0	11	1/f_{PS_A}
Δt_PD-PS	Part-to-Part Propagation delay variation SYNCN↑ to output toggling high⁽¹⁾	Fixed supply voltage, temp, and device setting⁽¹⁾			0	1	1/f _{PS_A}
OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
t_SK,LVDS	Skew between Y[7:4] LVDS	Y[7:4] = LVDS				40	ps
t_SK,LVDS	Skew between Y[3:0] LVDS	Y[3:0] = LVDS				40	ps
t_SK,LVDS	Skew between Y[7:0] LVDS	Y[7:0] = LVDS				80	ps
t_SK,CML	Skew between Y[3:0] CML	Y[3:0] = CML				40	ps
t_SK,PECL	Skew between Y[3:0] PECL	Y[3:0] = LVPECL				40	ps
t_SK,HCSL	Skew between Y[7:4] HCSL	Y[7:4] = HCSL				40	ps
t_SK,SE	Skew between Y[7:4] CMOS	Y[7:4] = CMOS				50	ps
OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
t_SK,CMOS-LVDS	Skew between Y[7:4] LVDS and CMOS mixed	Y[4] = CMOS, Y[7:5] = LVDS				2.5	ns
t_SK,CMOS-PECL	Skew between Y[7:0] CMOS and LVPECL mixed	Y[7:4] = CMOS, Y[3:0] = LVPECL				2.5	ns
t_SK,PECL-LVDS	Skew between Y[3:0] LVPECL and LVDS mixed	Y[0] = LVPECL, Y[3:1] = LVDS				120	ps
t_SK,PECL-CML	Skew between Y[3:0] LVPECL and CML mixed	Y[0] = LVPECL, Y[3:1] = CML				40	ps
t_SK,LVDS-PECL	Skew between Y[7:0] LVDS and LVPECL mixed	Y[7:4] = LVDS, Y[3:0] = LVPECL				180	ps
t_SK,LVDS-HCSL	Skew between Y[7:4] LVDS and HCSL mixed	Y[4] = LVDS, Y[7:5] = HCSL				250	ps
OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OutDiv = 3.125
t_{SK,DIFF, frac}	Skew between Y[7:4] LVDS using all fractional divider with the same divider setting	Y[7:4] = LVDS				200	ps

(1) SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).

8.20 Device Individual Block Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, T_A = –40°C to 85°C, Output Types = LVPECL/CML/LVDS/LVCMOS/HCSL

BLOCK	CONDITION	TYPICAL CURRENT CONSUMPTION (mA)
Core	CDCM6208V2G Core, active mode, PS_A = PS_B = 4	75
Output Buffer	CML output, AC coupled w/ 100 Ω diff load	24.25
	LVPECL, AC coupled w/ 100 Ω diff load	40
	LVCMOS output, transient, 'C _L' load, 'f' MHz output frequency, 'V' output swing	1.8 + V x f _OUT x (C _L+ 12 x 10 ^-12) x 10 ³
	LVDS output, AC coupled w/ 100 Ω diff load	19.7
	HCSL output, 50 Ω load to GND on each output pin	31
Output Divide Circuitry	Integer Divider Bypass (Divide = 1)	3
	Integer Divide Enabled, Divide > 1	8
	Fractional Divider Enabled	12
	additional current when PS_A differs from PS_B	15
Total Device, CDCM6208V2G	Device Settings (V2) PRI input enabled, set to LVDS mode SEC input XTAL Input bypass off, PRI only sent to PLL Reference clock 30.72 MHz PRI input divider set to 1 Reference input divider set to 1 Charge Pump Current = 2.5 mA VCO Frequency = 3.072 GHz PS_A = PS_B divider ration = 4 Feedback divider ratio = 25 Output divider ratio = 5 Fractional divider pre-divider = 2 Fractional divider core input frequency = 384 MHz Fractional divider value = 3.84, 5.76, 3.072, 7.68 CML outputs selected for CH0-3 (153.6 MHz) LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz, 125 MHz, 50 MHz)	(excl. I _{termination_resistors}) (1.8 V: 251 mA 2.5 V: 254 mA 3.3 V: 257 mA) (incl. I _{termination_resistors}) (1.8 V: 310 mA 2.5 V: 313 mA 3.3 V: 316 mA)
Total Device, CDCM6208V2G	Power Down (PDN = '0')	0.35

Helpful Note: The CDCM6208V2G User GUI does an excellent job estimating the total device current consumption based on the actual device configuration. Therefore, it is recommended to use the GUI to estimate device power consumption.

8.21 Worst Case Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 3.45 V, T_A = T-40°C to 85°C, Output Types = maximum swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation

BLOCK	CONDITION	CURRENT CONSUMPTION TYP / MAX
Total Device, CDCM6208V2G	All conditions over PVT, AC coupled outputs with all outputs terminated, device configuration: Device Settings (V2) PRI input enabled, set to LVDS mode SEC input XTAL Input bypass off, PRI only sent to PLL Reference clock 30.72 MHz PRI input divider set to 1 Reference input divider set to 1 Charge Pump Current = 2.5 mA VCO Frequency = 3.072 GHz PS_A = PS_B divider ration = 4 Feedback divider ratio = 25 Output divider ratio = 5 Fractional divider pre-divider = 2 Fractional divider core input frequency = 384 MHz Fractional divider value = 3.84, 5.76, 3.072, 7.68 CML outputs selected for CH0-3 (153.6 MHz) LVDS outputs selected for CH4-7 (100MHz, 66.66 MHz, 125 MHz, 50 MHz)	1.8 V: 310 mA / +21% (excl term) 3.3 V: 318 mA / +21% (excl term)

8.22 I²C TIMING⁽²⁾

PARAMETER		STANDARD MODE		FAST MODE		UNIT
PARAMETER		MIN	MAX	MIN	MAX	UNIT
f_SCL	SCL Clock Frequency	0	100	0	400	kHz
t_su(START)	START Setup Time (SCL high before SDA low)	4.7		0.6		μs
t_h(START)	START Hold Time (SCL low after SDA low)	4.0		0.6		μs
t_w(SCLL)	SCL Low-pulse duration	4.7		1.3		μs
t_w(SCLH)	SCL High-pulse duration	4.0		0.6		μs
t_h(SDA)	SDA Hold Time (SDA valid after SCL low)	0 ⁽¹⁾	3.45	0	0.9	μs
t_su(SDA)	SDA Setup Time	250		100		ns
t_r-in	SCL / SDA input rise time		1000		300	ns
t_f-in	SCL / SDA input fall time		300		300	ns
t_f-out	SDA Output fall time from V_IH min to V_IL max with a bus capacitance from 10 pF to 400 pF		250		250	ns
t_su(STOP)	STOP Setup Time	4.0		0.6		μs
t_BUS	Bus free time between a STOP and START condition	4.7		1.3		μs
t_{glitch_filter}	Pulse width of spikes suppressed by the input glitch filter	75	300	75	300	ns

(1) The I²C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.

(2) For additional information, refer to the I²C-Bus specification, Version 2.1 (January 2000); the CDCM6208V2G meets the switching characteristics for standard mode and fast mode transfer.

CDCM6208V2G CDCM6208_SPI_Port_Timing_SCAS931.gif

Figure 1. CDCM6208V2G SPI Port Timing

8.23 SPI Timing Requirements

PARAMETER		MIN	MAX	UNIT
f_Clock	Clock Frequency for the SCL		20	MHz
t₁	SPI_LE to SCL setup time	10		ns
t₂	SDI to SCL setup time	10		ns
t₃	SDO to SCL hold time	10		ns
t₄	SCL high duration	25		ns
t₅	SCL low duration	25		ns
t₆	SCL to SCS Setup time	10		ns
t₇	SCS Pulse Width	20		ns
t₈	SDI to SCL Data Valid (First Valid Bit after SCS)	10		ns

CDCM6208V2G I2C_Timing_Diagram_SCAS931.gif

Figure 2. I²C Timing Diagram

8.24 Typical Characteristics

CDCM6208V2G Fractional_divider_bit_jitter_300_SCAS931.png

f_FRAC = 300 MHz

Figure 3. Fractional Divider Bit Selection Impact on Jitter

CDCM6208V2G Fractional_divider_bit_TJ_SCAS931.gif

Figure 5. Fractional Divider Bit Selection Impact on T_J (Typical)

CDCM6208V2G PSRR_in_dBc_and_DJ_ps_SCAS931.gif

f _OUT = 122 MHz

Figure 7. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format

CDCM6208V2G Fractional_divider_input_frequency_jitter_SCAS931.png

Using Divide by x.73 Example

Figure 4. Fractional Divider Input Frequency Impact on Jitter

CDCM6208V2G Fractional_divider_bit_TJ_voltage_SCAS931.gif

Figure 6. Fractional Divider Bit Selection Impact on T_J
(Maximum Jitter Across Process, Voltage & Temperature)

8.24.1 Fractional Output Divider Jitter Performance

The fractional output divider jitter performance is a function of the fraction output divider input frequency as well as actual fractional divide setting itself. To minimize the fractional output jitter, it is recommended to use the least number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 3, the largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in the middle range of the fractional divider are selected. Tested using a LeCroy 40 Gbps RealTime scope over a time window of 200 ms. The R_J impact on T_J is estimated for a BERT 10^(–12) – 1. This measurement result is overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.

8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

See Figure 7 for reference.

Many system designs become increasingly more sensitive to power supply noise rejection. In order to simplify design and cost, the CDCM6208V2G has built in internal voltage regulation, improving the power supply noise rejection over designs with no regulators. As a result, the following output rejection is achieved:

The DJ due to PSRR can be estimated using Equation 1:

Equation 1. CDCM6208V2G eq_determin_cas931.gif

Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the according output jitter for a 122.88 MHz output signal with LVDS signaling could be estimated with DJ = 0.7ps.

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8 Specifications

8.1 Absolute Maximum Ratings(1)

8.2 ESD Ratings

8.3 Recommended Operating Conditions

8.4 Thermal Information, Airflow = 0 LFM(1) (2) (3) (4)

8.5 Thermal Information, Airflow = 150 LFM(1) (2) (3) (4)

8.6 Thermal Information, Airflow = 250 LFM(1) (2) (3) (4)

8.7 Thermal Information, Airflow = 500 LFM(1) (2) (3) (4)

8.8 Single Ended Input Characteristics

8.9 Single Ended Input Characteristics (PRI_REF, SEC_REF)

8.10 Differential Input Characteristics (PRI_REF, SEC_REF)

8.11 Crystal Input Characteristics (SEC_REF)

8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)

8.13 PLL Characteristics

8.14 LVCMOS Output Characteristics

8.15 LVPECL (High-Swing CML) Output Characteristics

8.16 CML Output Characteristics

8.17 LVDS (Low-Power CML) Output Characteristics

8.18 HCSL Output Characteristics

8.19 Output Skew and Sync to Output Propagation Delay Characteristics

8.20 Device Individual Block Current Consumption

8.21 Worst Case Current Consumption

8.22 I2C TIMING(2)

8.23 SPI Timing Requirements

8.24 Typical Characteristics

8.24.1 Fractional Output Divider Jitter Performance

8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

8.1 Absolute Maximum Ratings⁽¹⁾

8.4 Thermal Information, Airflow = 0 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

8.5 Thermal Information, Airflow = 150 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

8.6 Thermal Information, Airflow = 250 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

8.7 Thermal Information, Airflow = 500 LFM⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

8.22 I²C TIMING⁽²⁾