CSD87588N 同步降压 NexFET 电源块 II
- ZHCSAY0D March 2013 – April 2015 CSD87588N
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

CSD87588N 同步降压 NexFET 电源块 II

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

半桥电源块
电流 20A 时，系统效率达到 90%
高达 25A 的工作电流
高密度 - 5mm × 2.5mm 接合栅格阵列 (LGA) 封装
双侧冷却能力
超薄 - 最大厚度为 0.48mm
针对 5V 栅极驱动进行了优化
低开关损耗
低电感封装
符合 RoHS 环保标准
无卤素
无铅

2 应用范围

同步降压转换器
- 高电流、低占空比应用
多相位同步降压转换器
负载点 (POL) 直流 - 直流转换器

3 说明

此 CSD87588N NexFET™ 电源块 II 是针对同步降压应用的高度优化设计，能够在 5 mm × 2.5mm 的小外形尺寸封装内提供大电流和高效率。针对 5V 栅极驱动应用进行了优化，这款米6体育平台手机版_好二三四可提供高效且灵活的解决方案，在与外部控制器/驱动器的任一 5V 栅极驱动器成对使用时，均可提一个供高密度电源。

增加文本，调节间距
订购信息⁽¹⁾

器件	介质	数量	封装	出货
CSD87588N	13 英寸卷带	2500	5 x 2.5 LGA	卷带封装
CSD87588NT	7 英寸卷带	250	5 x 2.5 LGA	卷带封装

要了解所有可用封装，请见数据表末尾的可订购米6体育平台手机版_好二三四附录。

增加文本，调节间距

典型电路	典型电源块效率与功率损耗

4 修订历史记录

Changes from C Revision (June 2014) to D Revision

Changed capacitance units to read pF in Figure 15Go
Changed capacitance units to read pF in Figure 16Go

Changes from B Revision (January 2014) to C Revision

将“无铅引脚镀层”更改成了“无铅”Go

Changes from A Revision (May 2013) to B Revision

已添加小卷带信息Go
Updated Figure 5Go
Updated Figure 6Go
Updated Figure 7Go
Updated Figure 8Go
Changed figure reference to Figure 29 in electrical performanceGo

Changes from * Revision (March 2013) to A Revision

Changed R_θJC-PCBTo: R_θJC in the Thermal Information tableGo

5 Specifications

5.1 Absolute Maximum Ratings

T_A = 25°C (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
	Voltage	V_IN to P_GND	–0.8	30	V
		V_SW to P_GND		30
		V_SW to P_GND(10 ns)		32
		T_G to V_SW	–20	20
		B_G to P_GND	–20	20
I_DM	Pulsed Current Rating⁽²⁾			50	A
P_D	Power Dissipation⁽³⁾			6	W
E_AS	Avalanche Energy	Sync FET, I_D = 45, L = 0.1 mH		101	mJ
E_AS	Avalanche Energy	Control FET, I_D = 26, L = 0.1 mH		34	mJ
T_J	Operating Junction		–55	150	°C
T_stg	Storage Temperature Range		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Pulse Duration ≤50 µs, duty cycle ≤0.01

(3) Device mounted on FR4 material with 1 inch² (6.45 cm²) Cu

5.2 Recommended Operating Conditions

T_A = 25°C (unless otherwise noted)

			MIN	MAX	UNIT
V_GS	Gate Drive Voltage		4.5	16	V
V_IN	Input Supply Voltage			24	V
ƒ_SW	Switching Frequency	C_BST = 0.1 μF (min)	200	1500	kHz
	Operating Current	No Airflow		25	A
		With Airflow (200 LFM)		30	A
		With Airflow + Heat Sink		35	A
T_J	Operating Temperature			125	°C

5.3 Thermal Information

T_A = 25°C (unless otherwise stated)

THERMAL METRIC		MAX	UNIT
R_θJA	Junction-to-ambient thermal resistance (Min Cu) ⁽¹⁾	170	°C/W
R_θJA	Junction-to-ambient thermal resistance (Max Cu) ⁽²⁾⁽¹⁾	70
R_θJC	Junction-to-case thermal resistance (Top of package) ⁽¹⁾	3.7
R_θJC	Junction-to-case thermal resistance (P_GND Pin) ⁽¹⁾	1.25

(1) R_θJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. R_θJC is specified by design while R_θJA is determined by the user’s board design.

(2) Device mounted on FR4 material with 1 inch² (6.45 cm²) Cu.

5.4 Power Block Performance

T_A = 25°C (unless otherwise noted)

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
P_LOSS	Power Loss⁽¹⁾	V_IN = 12 V, V_GS = 5 V V_OUT = 1.3 V, I_OUT = 15 A ƒ_SW = 500 kHz L_OUT = 0.29 µH, T_J = 25ºC		2.1		W
I_QVIN	V_INQuiescent Current	T_G to T_GR = 0 V B_Gto P_GND = 0 V		10		µA

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins and using a high current 5 V driver IC.

5.5 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	Q1 FET			Q2 FET			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-Source Voltage	V_GS = 0 V, I_DS = 250 μA	30			30			V
I_DSS	Drain-to-Source Leakage Current	V_GS = 0 V, V_DS = 24 V			1			1	μA
I_GSS	Gate-to-Source Leakage Current	V_DS = 0 V, V_GS = 20			100			100	nA
V_GS(th)	Gate-to-Source Threshold Voltage	V_DS = V_GS, I_DS = 250 μA	1.1		1.9	1.1		1.9	V
R_DS(on)	Drain-to-Source On Resistance	V_GS = 4.5 V, I_DS = 15 A		10.4	12.5		3.5	4.2	mΩ
R_DS(on)	Drain-to-Source On Resistance	V_GS = 10 V, I_DS = 15 A		8	9.6		2.9	3.5	mΩ
g_ƒs	Transconductance	V_DS = 10 V, I_DS = 15 A		43			93		S
DYNAMIC CHARACTERISTICS
C_ISS	Input Capacitance ⁽¹⁾	V_GS = 0 V, V_DS = 15 V, ƒ = 1 MHz		566	736		2310	3000	pF
C_OSS	Output Capacitance ⁽¹⁾			341	444		682	887	pF
C_RSS	Reverse Transfer Capacitance ⁽¹⁾			10.3	13.4		62	80.4	pF
R_G	Series Gate Resistance ⁽¹⁾			1.2	2.4		1.1	2.2	Ω
Q_g	Gate Charge Total (4.5 V) ⁽¹⁾	V_DS = 15 V, I_DS = 15 A		3.2	4.1		13.7	17.9	nC
Q_gd	Gate Charge - Gate-to-Drain			0.7			4.3		nC
Q_gs	Gate Charge - Gate-to-Source			1.4			4.3		nC
Q_g(th)	Gate Charge at V_th			0.8			2.8		nC
Q_OSS	Output Charge	V_DD = 12 V, V_GS = 0 V		7			18.6		nC
t_d(on)	Turn On Delay Time	V_DS = 15 V, V_GS = 4.5 V, I_DS = 15 A, R_G = 2 Ω		7.3			12.1		ns
t_r	Rise Time			31.6			36.7		ns
t_d(off)	Turn Off Delay Time			10.2			20.1		ns
t_ƒ	Fall Time			5.0			6.3		ns
DIODE CHARACTERISTICS
V_SD	Diode Forward Voltage	I_DS = 15 A, V_GS = 0 V		0.85			0.78		V
Q_rr	Reverse Recovery Charge	V_dd = 15 V, I_F = 15 A, di/dt = 300 A/μs		12.5			26.7		nC
t_rr	Reverse Recovery Time	V_dd = 15 V, I_F = 15 A, di/dt = 300 A/μs		16			23		ns

(1) Specified by design

Max R_θJA = 70°C/W when mounted on 1 inch² (6.45 cm²) of
2 oz. (0.071 mm thick) Cu.

Max R_θJA = 170°C/W when mounted on minimum pad area of
2 oz. (0.071 mm thick) Cu.

5.6 Typical Power Block Device Characteristics

T_J = 125°C, unless stated otherwise.The Typical Power Block System Characteristic curves Figure 3 and Figure 4 are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6 copper layers of 1 oz. copper thickness. See Application and Implementation for detailed explanation.

Figure 1. Power Loss vs Output Current

Figure 3. Safe Operating Area – PCB Horizontal Mount

Figure 2. Normalized Power Loss vs Temperature

Figure 4. Typical Safe Operating Area

Figure 5. Normalized Power Loss vs Switching Frequency

Figure 7. Normalized Power Loss vs Output Voltage

Figure 6. Normalized Power Loss vs Input Voltage

Figure 8. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

T_A = 25°C, unless stated otherwise.

Figure 9. Control MOSFET Saturation

Figure 11. Control MOSFET Transfer

Figure 13. Control MOSFET Gate Charge

Figure 15. Control MOSFET Capacitance

Figure 17. Control MOSFET V_GS(th)

Figure 19. Control MOSFET R_DS(on) vs V_GS

Figure 21. Control MOSFET Normalized R_DS(on)

Figure 23. Control MOSFET Body Diode

Figure 25. Control MOSFET Unclamped Inductive Switching

Figure 10. Sync MOSFET Saturation

Figure 12. Sync MOSFET Transfer

Figure 14. Sync MOSFET Gate Charge

Figure 16. Sync MOSFET Capacitance

Figure 18. Sync MOSFET V_GS(th)

Figure 20. Sync MOSFET R_DS(on) vs V_GS

Figure 22. Sync MOSFET Normalized R_DS(on)

Figure 24. Sync MOSFET Body Diode

Figure 26. Sync MOSFET Unclamped Inductive Switching

6 Application and Implementation

6.1 Application Information

The CSD87588N NexFET power block is an optimized design for synchronous buck applications using 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored toward a more systems-centric environment. System-level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application.

6.1.1 Power Loss Curves

MOSFET-centric parameters such as R_DS(ON) and Q_gd are needed to estimate the loss generated by the devices. To simplify the design process for engineers, TI has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87588N as a function of load current. This curve is measured by configuring and running the CSD87588N as it would be in the final application (see Figure 27). The measured power loss is the CSD87588N loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. (V_IN × I_IN) + (V_DD × I_DD) – (V_{SW_AVG} × I_OUT) = Power Loss

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions.

6.1.2 Safe Operating Curves (SOA)

The SOA curves in the CSD87588N data sheet provide guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness.

6.1.3 Normalized Curves

The normalized curves in the CSD87588N data sheet provides guidance on the Power Loss and SOA adjustments based on their application-specific needs. These curves show how the power loss and SOA boundaries adjust for a given set of systems conditions. The primary y-axis is the normalized change in power loss and the secondary y-axis is the change in system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve.

Figure 27. Typical Application

6.1.4 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure outlines the steps the user should take to predict product performance for any set of system conditions.

6.1.4.1 Design Example

Operating Conditions:

Output Current = 15 A
Input Voltage = 7 V
Output Voltage = 1 V
Switching Frequency = 800 kHz
Inductor = 0.2 µH

6.1.4.2 Calculating Power Loss

Power Loss at 15 A = 2.75 W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.03 (Figure 6)
Normalized Power Loss for output voltage ≈ 0.94 (Figure 7)
Normalized Power Loss for switching frequency ≈ 1.08 (Figure 5)
Normalized Power Loss for output inductor ≈ 1.03 (Figure 8)
Final calculated Power Loss = 2.75 W × 1.05 × 0.95 × 1.05 × 1.05 ≈ 3.02 W

6.1.4.3 Calculating SOA Adjustments

SOA adjustment for input voltage ≈ 0.3ºC (Figure 6)
SOA adjustment for output voltage ≈ –0.5ºC (Figure 7)
SOA adjustment for switching frequency ≈ 0.7ºC (Figure 5)
SOA adjustment for output inductor ≈ 0.3ºC (Figure 8)
Final calculated SOA adjustment = 0.3 + (–0.5) + 0.7 + 0.3 ≈ 0.8ºC

In the previous design example, the estimated power loss of the CSD87588N would increase to 3.02 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 0.8ºC. Figure 28 graphically shows how the SOA curve would be adjusted accordingly.

Start by drawing a horizontal line from the application current to the SOA curve.
Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 0.8ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.

Figure 28. Power Block SOA