7.3 Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As V_VDD rises, both the control FET and sync FET gates hold actively low at all times until V_VDD reaches the higher UVLO threshold (V_{UVLO_H}). Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold (V_{UVLO_L} = V_{UVLO_H} – hysteresis), the device disables the driver and drives the outputs of the control FET and sync FET gates actively low. Figure 12 shows this function.

Figure 12. UVLO Operation