ZHCSAO1D January 2013 – August 2016 CSD97374Q4M
The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.
Table 1 shows the logic functions of UVLO, PWM, SKIP#, the control FET gate and the sync FET gate.
| UVLO | PWM | SKIP# | SYNC FET GATE | CONTROL FET GATE | MODE |
|---|---|---|---|---|---|
| Active | — | — | Low | Low | Disabled |
| Inactive | Low | Low | High(1) | Low | DCM(1) |
| Inactive | Low | High | High | Low | FCCM |
| Inactive | High | H or L | Low | High | |
| Inactive | Tri-state | H or L | Low | Low | LQ |
| Inactive | — | Tri-state | Low | Low | ULQ |