9.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below is a brief description on how to address each parameter.

9.1.2 Electrical Performance

The CSD97395Q4M has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

• The placement of the input capacitors relative to V_IN and P_GND pins of CSD97395Q4M device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the V_IN and P_GND pins (see Figure 16). The example in Figure 16 uses 1 × 1 nF 0402 25 V and 3 × 10 µF 1206 25 V ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C5, C8 and C6, C19 should follow in order.
• The bootstrap cap C_BOOT 0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT and BOOT_R pins
• The switching node of the output inductor should be placed relatively close to the Power Stage CSD97395Q4M V_SW pins. Minimizing the V_SW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. ⁽¹⁾