SNAS321G June 2005 – April 2016 DAC101S101 , DAC101S101-Q1
PRODUCTION DATA.
| PIN | I/O(1) | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | DAC101S101 | DAC101S101-Q1 | |||
| SOT-23 | VSSOP | SOT-23 | |||
| DIN | 4 | 7 | 4 | I | Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. |
| GND | 2 | 8 | 2 | G | Ground reference for all on-chip circuitry. |
| NC | – | 2,3 | – | – | No Connect. There is no internal connection to these pins. |
| SCLK | 5 | 6 | 5 | I | Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. |
| SYNC | 6 | 5 | 6 | I | Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. |
| VA | 3 | 1 | 3 | S | Power supply and Reference input. Should be decoupled to GND. |
| VOUT | 1 | 4 | 1 | O | DAC Analog Output Voltage. |