8.3.1 Output Amplifiers

The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to V_A when the reference is V_A. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and V_A, in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than V_A, there is only a loss in linearity in the lowest codes. The output capabilities of the amplifier are described in Electrical Characteristics.

The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to V_A. The zero-code and full-scale outputs for given load currents are available in Electrical Characteristics.

8.3.2 Reference Voltage

The DAC104S085 uses a single external reference that is shared by all four channels. The reference pin, V_REFIN, is not buffered and has an input impedance of 30 kΩ. TI recommends driving the V_REFIN by a voltage source with low output impedance. The reference voltage range is 1 V to V_A, providing the widest possible output dynamic range.

8.3.3 Power-On Reset

The power-on reset circuit controls the output voltages of the four DACs during power up. Upon application of power, the DAC registers are filled with zeros and the output voltages are 0 V. The outputs remain at 0 V until a valid write sequence is made to the DAC.

8.4.1 Power-Down Modes

The DAC104S085 has four power-down modes, two of which are identical. In power-down mode, the supply current drops to 20 µA at 3 V and 30 µA at 5 V. The DAC104S085 is set in power-down mode by setting OP1 and OP0 to 11. Because this mode powers down all four DACs, the address bits, A1 and A0, are used to select different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tri-stated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by
2.5 kΩ or 100 kΩ to ground respectively (see Table 1).

The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC registers are unaffected when in power down. Each DAC register maintains its value prior to the DAC104S085 being powered down unless it is changed during the write sequence that instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with SYNC and D_IN idled low and SCLK disabled. The time to exit power down (Wake-Up Time) is typically t_WU µs as stated in Timing Requirements.

8.4.2 Bipolar Operation

The DAC104S085 is designed for single-supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 27. This circuit provides an output voltage range of ±5 V. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5 V.

Figure 27. Bipolar Operation

The output voltage of this circuit for any code is found in Equation 2 and Equation 3.

A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.

8.5.1 Serial Interface

The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. See the Figure 1 for information on a write sequence.

A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D_IN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register, it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Figure 1). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel address, mode of operation and/or register contents) is executed. At this point the SYNC line may be kept low or brought high. Any data and clock pulses after the 16th falling clock edge is ignored. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of SYNC.

Because the SYNC and D_IN buffers draw more current when they are high, they must be idled low between write sequences to minimize power consumption.

8.5.2 Input Shift Register

The input shift register, Figure 28, has sixteen bits. The first two bits are address bits. They determine whether the register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that determine the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The data format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s corresponding to a full-scale output of V_REFIN – 1 LSB. The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Figure 1.

Figure 28. Input Register Contents

Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and there is no change in the mode of operation or in the DAC output voltages.

8.5.3 DSP and Microprocessor Interfacing

Interfacing the DAC104S085 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process.

8.5.3.1 ADSP-2101 and ADSP2103 Interfacing

Figure 29 shows a serial interface between the DAC104S085 and the ADSP-2101 or ADSP2103. The DSP must be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.

Figure 29. ADSP-2101 and ADSP2103 Interface

8.5.3.2 80C51 and 80L51 Interface

Figure 30 shows a serial interface between the DAC104S085 and the 80C51/80L51 microcontroller. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown in Figure 30 uses port line P3.3. This line is taken low when data is transmitted to the DAC104S085. Because the 80C51 and 80L51 transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51 and 80L51 transmit routine must recognize that the 80C51 and 80L51 transmits data with the LSB first while the DAC104S085 requires data with the MSB first.

Figure 30. 80C51 and 80L51 Interface

8.5.3.3 68HC11 Interface

Figure 31 shows a serial interface between the DAC104S085 and the 68HC11 microcontroller. The SYNC line of the DAC104S085 is driven from a port line (PC7 in Figure 31), similar to the 80C51/80L51.

The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 must be raised to end the write sequence.

Figure 31. 68HC11 Interface

8.5.3.4 Microwire Interface

Figure 32 shows an interface between a Microwire compatible device and the DAC104S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before driving the SCLK of the DAC104S085.

Figure 32. Microwire Interface