ZHCSPG5 December   2021 DAC11001B

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. 6.7  Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. 6.8  Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. 6.9  Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter Architecture
      2. 7.3.2 External Reference
      3. 7.3.3 Output Buffers
      4. 7.3.4 Internal Power-On Reset (POR)
      5. 7.3.5 Temperature Drift and Calibration
      6. 7.3.6 DAC Output Deglitch Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fast-Settling Mode and THD
      2. 7.4.2 DAC Update Rate Mode
    5. 7.5 Programming
      1. 7.5.1 Daisy-Chain Operation
      2. 7.5.2 CLR Pin Functionality and Software Clear
      3. 7.5.3 Output Update (Synchronous and Asynchronous)
        1. 7.5.3.1 Synchronous Update
        2. 7.5.3.2 Asynchronous Update
      4. 7.5.4 Software Reset Mode
    6. 7.6 Register Map
      1. 7.6.1 NOP Register (address = 00h) [reset = 0x000000h for bits [23:0]]
      2. 7.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h for bits [23:0]]
      3. 7.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
      4. 7.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
      5. 7.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
      6. 7.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
      7. 7.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Source Measure Unit (SMU)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 High-Precision Control Loop
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Arbitrary Waveform Generation (AWG)
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Interfacing to a Processor
      2. 8.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 8.3.3 Embedded Resistor Configurations
        1. 8.3.3.1 Minimizing Bias Current Mismatch
        2. 8.3.3.2 2x Gain Configuration
        3. 8.3.3.3 Generating Negative Reference
    4. 8.4 What to Do and What Not to Do
      1. 8.4.1 What to Do
      2. 8.4.2 What Not to Do
    5. 8.5 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Assembly Effects on Precision
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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10.1.1 PCB Assembly Effects on Precision

The printed-circuit board (PCB) assembly process, including reflow soldering, imparts thermal stresses on the device which can degrade the precision of the device and must be considered in the development of very-high-precision systems. Standard reflow guidelines must be followed to achieve the device specified performance. For more information please see Texas Instruments, MSL Ratings and Reflow Profiles application report.

Baking the PCBs after the assembly process can restore the precision of the device to pre-assembly values. Figure 10-1 to Figure 10-3 show the effect of reflow soldering on the typical distribution of INL of the device.

Figure 10-1 shows the INL distribution for a set of DAC11001B devices before the PCB assembly process. Exposing the devices to a JEDEC-standard thermal profile for reflow soldering produces the histogram shown in Figure 10-2 on another set of devices. The standard INL deviation increased due to the thermal stress imparted to the device from the reflow process. However, baking DAC11001B units for 60 minutes at 125°C after the reflow soldering process produced the distribution given in Figure 10-3. The post-reflow bake restored the INL standard deviation to pre-assembly levels.

Figure 10-1 Typical INL Distribution Before Reflow Soldering
Figure 10-3 Typical INL Distribution Post-Reflow Units Baked at 125°C for 60 Minutes
Figure 10-2 Typical INL Distribution After Reflow Soldering
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