Table 2. Symbol Set Table

Character Mnemonic	SWIF Symbol	Comments
“0”		Occupies one symbol period Transmit from Master only 25% duty-cycle square waveform Terminates LOW
“1”		Occupies one symbol period Transmit from Master only 75% duty-cycle square waveform Terminates LOW
“D”		Occupies one symbol period Transmit from Master only 50% duty-cycle square waveform Terminates LOW
“A”		Occupies two symbol periods Master stops driving the SWIF and “listens” for acknowledge pulse from the Slave Slave pulls ACKB LOW to reverse the direction of data flow through the transformer Slave's DBACK will drive the SWIF pri_rx line between 50% points of the adjacent periods - in this interval Master must de-assert pri_tx_en_n Terminates with pri_tx = LOW and pri_tx_en_n = LOW
“L”		Occupies one symbol period, but can be repeated indefinitely Transmit from Master only Always LOW Does not carry any meaningful information Used as an inter-frame symbol, i.e., sent by the Master between valid data frames

7.5.1.4.1 Transformer Coupled Interface - Data Flow to the DAC

In systems requiring galvanic isolation between the transmitter (micro-controller) and the receiver, the commonly used coupling element is a pulse transformer. Transformer passes only the AC components of the square input waveform resulting in an impulse train across the secondary winding. Buffers A and B form a latch circuit around the secondary winding that recovers the square waveform from the impulse train.

Figure 15 shows the details of the square waveform transmission from the primary side and recovery of the signal on the secondary side. Transmitter’s DC component is blocked by the capacitor CP. The transmitter’s output waveform VO results in the impulse train VP across the primary winding. Similar impulse train then appears across the secondary winding. If the magnitude of the impulse exceeds the threshold on the A buffer, the latch formed by A and B buffers will change state. The new latch state will persist until an opposite polarity impulse appears across the secondary winding.

Note that in Figure 15 the capacitor CS bottom plate floats, and thus does not affect the operation of this circuit.

Figure 15. Transformer-Coupled SWIF Link With the DAC161P997 as Receiver

7.5.1.4.2 Transformer Coupled Interface - Acknowledge Pulse

Since the transformer is a symmetrical device (particularly one with 1:1 winding ratio), it is simple to reverse the data flow through it.

Figure 16 shows the SWIF interface circuit during the transmission of the Acknowledge pulse from the DAC161P997 on the secondary side back to the micro-controller on the primary side.

On the secondary side buffer B drives the square waveform across the transformer. Capacitor CS, whose bottom plate is now grounded via the ACKB pin, blocks the DC component of the square waveform. Buffer A is inactive.

On the primary side a square waveform recovery is performed by the now familiar latch.

Figure 16. Transformer-Coupled SWIF Link With the DAC161P997 as Transmitter

7.5.1.4.3 DC-Coupled Interface

DC coupled signal path between the transmitter and the receiver is shown in Figure 17. Such circuit as the internal buffer A is sufficient for the signal recovery as the signal presented at the DIN input is a square CMOS level waveform.

In noisy environments it may be necessary to implement a Hysteresis loop around the DIN input to improve noise immunity of the input circuit. Presence of the buffer C and its output resistor facilitate this. The Hysteresis can be easily realized by inserting R_IN between the transmitter and DIN input.

Note that when R_IN = 0 the presence of the buffer C can be ignored.

Figure 17. DC-Coupled SWIF Input

7.5.1.4.4 Transformer Selection and SWIF Data Link Circuit Design

In general, the transformers developed for T1/E1 telecom applications are well suited as the interface element for the DAC161P997 in the galvanically isolated industrial transmitter. The application circuit schematic utilizing T1/E1 transformer as the isolation element is shown in Typical Application. A number of suggested off the shelf transformers are listed in Table 3.

Model suitable for simulating the behavior of the pulse transformer is shown in Figure 18. The model parameters are readily available in the datasheets provided by the transformer manufacturers, see Table 3 for examples.

Figure 18. Pulse Transformer Model - Winding Ratio 1:1

The circuit behavior will be dominated by the DC blocking capacitance C_P and the magnetizing inductance L_M. In the example circuit shown in Figure 19 the rising edge of VO ultimately results in an impulse at the input DIN, see Figure 20. Once voltage at DIN is above VIH of the A buffer, the A buffer will change its state. However, the latch will acquire a new state only if the voltage at DIN persists above VIH for T_PEAK > TD.

The parasitic elements in the transformer model: L_LS, L_SP, C_WS, C_WP may result in the oscillating component superimposed on the dominant impulse response waveform shown in Figure 20. The oscillation should be controlled so that the condition T_PEAK> TD is maintained. The typical method for controlling this parasitic oscillation is to insert a damping element into the signal path. A small resistance in series with transformer winding is such damping element. The typical application example in Typical Application illustrates this.

The delay around the SWIF input latch, from DIN to DBACK, TD is specified in Electrical Characteristics.

Figure 19. NRZ Waveform Transmission and Recovery Circuit Model

Figure 20. SWIF Link Circuit Response to Step-Input