10.1 Layout Guidelines

To maximize the performance of the DAC161S997 in any application, good layout practices and proper circuit design must be followed. A few recommendations specific to the DAC161S997 are:

• Make sure that VD and VA have decoupling capacitors local to the respective terminals.
• Minimize trace length between the C1, C2, and C3 capacitors and the DAC161S997 pins.

10.2 Layout Example

Figure 34 and Figure 35 show the DAC161S997 evaluation module (EVM) layout

Figure 34. Example PCB layout: Top Layer

Figure 35. Example PCB layout: Bottom Layer