11.1 Layout Guidelines

To maximize the performance of the DAC161S997 in any application, good layout practices and proper circuit design must be followed. A few recommendations specific to the DAC161S997 are:

• Make sure that VD and VA have decoupling capacitors local to the respective terminals.
• Minimize trace length between the C1, C2, and C3 capacitors and the DAC161S997 pins.

11.2 Layout Example

Figure 30 to Figure 32 show the DAC161S997 evaluation module (EVM) layout

Figure 30. Example PCB layout: Top Assembly Layer

Figure 31. Example PCB layout: Top Layer

Figure 32. Example PCB layout: Bottom Layer