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ZHCSDM6A JUNE 2013 – December 2014 DAC161S997

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

RGH|16
- MPQF182B

散热焊盘机械数据 (封装 | 引脚)

RGH|16
- QFND440A

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7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
Supply voltage (VA, VD to COMA, COMD)	–0.3	6	V
Voltage between any two pins⁽²⁾		6	V
Current IN or OUT of any pin — except OUT pin⁽³⁾		5	mA
Output current at OUT		50	mA
Junction Temperature		150	°C
Operating Temperature	–40	105	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to COMA = COMD = 0 V, unless otherwise specified.

(3) When the input voltage (VIN) at any pin exceeds power supplies (VIN < COMA or VIN > VA), the current at that pin must not exceed 5 mA, and the voltage (VIN) at that pin relative to any other pin must not exceed 6 V. See for Pin Descriptions for additional details of input structures.

(4) The Human Body Model (HBM) is a 100 pF capacitor charged to the specified voltage then discharged through a 1.5 kΩ resistor into each pin.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽⁴⁾	2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

		MIN	MAX	UNIT
	BASE load to COMA	0	15	pF
	(COMA - COMD)		0	V
	OUT load to COMA		none
	(VA - VD)		0	V
VA, VDD	Supply voltage	2.7	3.6	V
T_A	Temperature	–40	105	°C

7.4 Thermal Information

		DAC161S997	UNIT
		WQFN
		16 PINS
R_θJA	Package thermal impedance⁽¹⁾	35	°C/W

(1) The package thermal impedance is calculated in accordance with JESD 51-7.

7.5 Electrical Characteristics

Unless otherwise noted, these specifications apply for VA = VD = 3.3 V, COMA = COMD = 0 V, T_A= 25°C, external bipolar transistor: 2N3904, RE = 22 Ω, C1 = C2 = C3 = 2.2 nF.

PARAMETER		TEST CONDITIONS	MIN⁽⁷⁾	TYP	MAX⁽⁷⁾	UNIT
POWER SUPPLY
VA, VD	Supply voltage	VA = VD -40°C ≤ T_A ≤ 105°C	2.7		3.6	V
	VA supply current	DACCODE = 0x0200⁽¹⁾		43		µA
	VD supply current			57		µA
ICC	Total supply current			100	125	µA
DC ACCURACY
N	Resolution			16		bits
INL	Integral non-linearity⁽⁶⁾	0x2AAA < DACCODE < 0xD555 (4 mA < I_LOOP < 20 mA)	–1.5		2.6	µA
DNL	Differential non-linearity	see ⁽²⁾	–0.2		0.2	µA
TUE	Total unadjusted error	0x2AAA < DACCODE < 0xD555		0.01		%FS
OE	Offset error	see ⁽³⁾	–7.86	0.84	7.86	µA
ΔOE	Offset error temperature coefficient	-40°C ≤ T_A ≤ 105°C		0.48		ppmFS/°C
GE	Gain error	see ⁽⁴⁾		0.007		%FS
ΔGE	Gain error temperature coefficient	-40°C ≤ T_A ≤ 105°C		5		ppmFS/°C
IERRL	LOW ERROR current	ERR_LOW = default	3.36	3.375	3.39	mA
IERRH	HIGH ERROR current	ERR_HIGH = default	21.70	21.75	21.82	mA
LTD	Long term drift — mean shift of 12 mA output current after 1000 hours at 150°C			90		ppmFS
LOOP CURRENT OUTPUT (OUT)
I_OUTMIN	Minimum output current	Tested at DACCODE = 0x01C2⁽⁵⁾			0.19	mA
I_OUTMAX	Maximum output current	Tested at DACCODE = 0xFFFF	23.95			mA
R_OUT	Output impedance			200		MΩ
	COMA to OUT voltage drop	I_OUT = 24 mA		960		mV
BASE OUTPUT
I_OUTSC	BASE short circuit output current	BASE forced to COMA potential		10		mA
DYNAMIC CHARACTERISTICS
	Output noise density	1 kHz		20		nA/rtHz
	Integrated output noise	1 Hz to 1 kHz band		300		nA_RMS
INTERNAL TIMER
TM	Timeout period	Default setting of TIMEOUT in CONFIG register		100		ms
DIGITAL INPUT CHARACTERISTICS
I_IN	Digital input leakage current		–10		10	µA
V_IL	Input low voltage				0.2 × VD	V
V_IH	Input high voltage		0.7 × VD			V
C_IN	Input capacitance			5		pF
DIGITAL OUTPUT CHARACTERISTICS
V_OL	Output Low voltage	I_sink = 200 μA			0.4	V
V_OH	Output HIGH voltage	I_sink = 200 μA	2.6			V
I_OZH, I_OZL	TRI-STATE leakage current		–10		10	µA
C_OUT	TRI-STATE output capacitance			5		pF

(1) At code 0x0200 the BASE current is minimal, for example, device current contribution to power consumption is minimized. SPI is inactive, for example, after transmitting code 0x200 to the DAC161S997, there are no more transitions in the channel during the supply current measurement.

(2) Specified by design.

(3) Offset is the y-intercept of the straight line defined by 4 mA and 20 mA points of the measured transfer characteristic.

(4) Gain Error is the difference in slope of the straight line defined by measured 4 mA and 20 mA points of transfer characteristic, and that of the ideal characteristic.

(5) This must be treated as the minimum LOOP current ensured in self-powered mode.

(6) INL is measured using the best-fit method in the output current range of 4 mA to 20 mA.

(7) Limits are ensured by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.

7.6 Timing Requirements

		MIN	NOM	MAX	UNIT
f_CLK	SCLK frequency	0		10	MHz
t_H	SCLK high time	0.4 / F_CLK	50		ns
t_L	SCLK low time	0.4 / F_CLK	50		ns
t_CSB	CSB pulse width	5	40		ns
t_CSS	CSB set-up time prior to SCLK rising edge	5			ns
t_SCH	24th rising edge of SCLK to CSB rising edge	15			ns
t_CSH	CSB hold time after the 24th falling edge of SCLK	6	10		ns
t_ZSDO	CSB falling edge to SDO valid		10	35	ns
t_SDOZ	CSB rising edge to SDO HiZ		10		ns
t_DS	SDI data set-up time prior to SCLK rising edge	10			ns
t_DH	SDI data hold time after SCLK rising edge	6	10		ns
t_DO	SDO output data valid			30	ns

Figure 1. SPI Timing Diagrams

7.7 Typical Characteristics

Unless otherwise noted, data presented here was collected under these conditions VA = VD = 3.3 V, T_A = 25°C, external bipolar transistor: 2N3904, RE = 22 Ω, C1 = C2 = C3 = 2.2 nF.