The following startup sequence is recommended to power-up the DAC3482:

1. Set TXENABLE low
2. Supply all 1.2V voltages (DACVDD, DIGVDD, CLKVDD, and VFUSE) and all 3.3V voltages (AVDD, IOVDD, and PLLAVDD). The 1.2-V and 3.3-V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after the SIF register programming.
4. Toggle the RESETB pin for a minimum 25ns active low pulse width.
5. Program the SIF registers.
6. Program config1, bit <8> = 0b and config16, bit <13:12> = 11b.
7. Program fuse_sleep (config 27, Bit <11> ) to put internal fuses to sleep.
8. FIFO configuration needed for synchronization:
   1. Program syncsel_fifoin(3:0) (config32, bit<15:12>) to select the FIFO input pointer sync source.
   2. Program syncsel_fifoout(3:0) (config32, bit<11:8>) to select the FIFO output pointer sync source.
   3. Program syncsel_dataformatter(1:0) (config31, bit<3:2>) to select the FIFO Data Formatter sync source.
9. Clock divider configuration needed for synchronization:
   1. Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source.
   2. Program clkdiv_sync_ena (config0, bit<2>) to 1b to enable clock divider sync.
   3. For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit<11>) to 1b to synchronize the PLL N-divider.
10. Provide all LVDS inputs (D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N) simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
    1. For Single Sync Source Mode where either FRAMEP/N or SYNCP/N is used to sync the FIFO, a single rising edge for FIFO, FIFO data formatter, and clock divider sync is recommended. Periodic sync signal is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer.
    2. For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.
    3. For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL N-divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as long as the t_{(SYNC_PLL)} setup and hold timing requirement is met with respect to the reference clock source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point.
11. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed for synchronization:
    1. For Single Sync Source Mode where the clock divider sync source is either FRAMEP/N or SYNCP/N, clock divider syncing may be disabled after DAC3482 initialization and before the data transmission by setting clkdiv_sync_ena (config0, bit 2) to 0b. This is to prevent accidental syncing of the clock divider when sending FRAMEP/N or SYNCP/N pulse to other digital blocks.
    2. For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time.
    3. Optionally, to prevent accidental syncing of the FIFO and FIFO data formatter when sending the FRAMEP/N or SYNCP/N pulse to other digital blocks such as NCO, QMC, ..., disable FIFO syncing by setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000b after the FIFO input and output pointers are initialized. Also Disable the FIFO data formatter by setting syncsel_dataformatter(1:0) to 10b or 11b. If the FIFO and FIFO data formatter sync remain enabled after initialization, the FRAMEP/N or SYNCP/N pulse must occur in ways to not disturb the FIFO operation. Refer to the Section 6.3.3 for detail.
    4. Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit<11>) to 0b.
12. Enable transmit of data by asserting the TXENABLE pin or set sif_txenable to 1b.
13. At any time, if any of the clocks (DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 8 through 12. Program the FIFO configuration and clock divider configuration per steps 8 and 9 appropriately to accept the new sync pulse or pulses for the synchronization.