In this mode the clock at the DACCLK input functions as a reference clock source to the on-chip PLL. The on-chip PLL will then multiply this reference clock to supply a higher frequency DAC sample rate clock. Figure 6-8 shows the block diagram of the PLL circuit.

Figure 6-8 PLL Block Diagram

The DAC3482 PLL mode is selected by setting the following:

1. pll_ena bit in register config24 to 1b to route to the PLL clock path.
2. pll_sleep bit in register config26 to 0b to enable the PLL and VCO.

The output frequency of the VCO is designed to be the in the range from 3.3 GHz to 4.0 GHz. The prescaler value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse tune bits, pll_vco(5:0) in register config26, can adjust the center frequency of the VCO towards the product of the prescaler value and DAC sample rate clock. Figure 6-9 shows a typical relationship between coarse tune bits and VCO center frequency. For the recommended pll_vco(5:0) setting over free-air temperature, refer to Section 5.8 for details.

Figure 6-9 Typical PLL/VCO Lock Range vs Coarse Tuning Bits

If the corresponding pll_vco(5:0) setting and the VCO frequency of interest are not in Section 5.8, TI recommends the use of the typical pll_vco(5:0) value found in Figure 6-9 along with implementation of PLL lock status check over temperature. The PLL lock status can be read back in pll_lfvolt(2:0) register of config24. If the PLL is out of range, adjust pll_vco(5:0) in config26 accordingly. The example PLL lock status and adjustment algorithm can be found in Figure 6-10.

Figure 6-10 Example PLL Lock Status and Adjustment Algorithm

Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 983.04MHz, ...) are generated from this VCO frequency in conjunction with the pre-scaler setting as shown in Table 6-4.

The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.

The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N dividers can keep the PFD frequency below 155MHz for peak operation.

The overall divide ratio inside the loop is the product of the Pre-Scale and M dividers (P * M) and the following guidelines should be followed:

• The overall divide ratio range is from 24 to 480
• When the overall divide ratio is less than 120, the internal loop filter provides a stable loop
• When the overall divide ratio is greater than 120, an external loop filter or double charge pump is required for loop stability

The single- and double-charge-pump current option are selected by setting pll_cp in register config24 to 01b and 11b, respectively. When using the double-charge-pump setting, an external loop filter is not required. If an external filter is required, the following filter should be connected to the LPF pin (A1 for RKD package and D12 for ZAY package):

Figure 6-11 Recommended External Loop Filter

The PLL will generate an internal OSTR signal and does not require the external LVPECL OSTR signal. The OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same as the PFD frequency. Therefore, using PLL with Dual Sync Sources mode requires the PFD frequency to be the pre-defined OSTR frequency listed in Section 6.3.3. This will allow the FIFO to be synced correctly by the internal OSTR.