The DAC3482 includes a 2-channel, 16-bits wide, and 8-samples deep input FIFO which acts as an elastic buffer. The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data rate clock such as the ones resulting from clock-to-data variations from the data source.

Figure 6-5 shows a simplified block diagram of the FIFO. The following sections provide brief overviews of the FIFO, device synchronization, and device clocking. For more details of the topics, refer to application report SLAA584.

Figure 6-5 DAC3482 FIFO Block Diagram

Data is written to the device on the rising and falling edges of DATACLK. Each 32-bit wide sample (16-bit I-data and 16-bit Q-data) is written into the FIFO at the address indicated by the write pointer. Similarly, data from the FIFO is read by the FIFO Out Clock 32-bits at a time from the address indicated by the read pointer. The FIFO Out Clock is generated internally from the DACCLK signal. Its rate is equal to DACCLK/2/Interpolation for word-wide data transmission, or DACCLK/Interpolation for byte-wide data transmission. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the next address.

The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in Figure 6-5. This offset gives optimal margin within the FIFO. The default read pointer location can be set to another value using fifo_offset(2:0) in register config9 (address 4 by default). Under normal conditions data is written-to and read-from the FIFO at the same rate and consequently the write and read pointer gap remains constant. If the FIFO write and read rates are different, the corresponding pointers will be cycling at different speeds which could result in pointer collision. Under this condition the FIFO attempts to read and write data from the same address at the same time which will result in errors and thus must be avoided.

The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either FRAME or SYNC is used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.

Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be set to reset the read pointer as well. In this case, the FIFO Out clock recaptures the write pointer sync signal to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of the reset signal, and will create latency variation based on the capture edge of the FIFO Out Clock. Since the reset signal also synchronizes the clock divider circuit for the FIFO Out clock generation, the latency variation also includes the capture edge of the DACCLK cycle in the clock divider stage. Ultimately, the variation in capture edge of both the FIFO Out clock and the DACCLK limits the precise control of the output timing latency. The full latency control of the DAC will be difficult and is not recommended in this setup.

To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. To minimize the skew, it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 or LMK0480x family to provide the DACCLK and OSTR signals to all the DAC3482 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones establishes proper phase relationship.

The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, the signals to sync the FIFO read and write pointer can repeat at multiples of 8 FIFO samples when the data interface is byte-wide format. When the data interface is word-wide format, the signal to sync the FIFO read and write pointer can repeat at multiples of 16 FIFO samples.

The frequency limitation for FRAME and SYNC signals are the following:

where n = 1, 2, … can repeat multiples of 8 FIFO samples for Byte-Wide Mode

where n = 1, 2, … can repeat multiples of 16 FIFO samples for Word-Wide Mode

The frequency limitation for the OSTR signal is the following:

where n = 1, 2, … can repeat multiples of 8 FIFO samples for Byte-Wide Mode

where n = 1, 2, … can repeat multiples of 16 FIFO samples for World-Wide Mode

The frequencies above are at maximum when n = 1. This is when the FRAME, SYNC, or OSTR have a rising edge transition every 8 or 16 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every n × 8 or n × 16 FIFO samples.

Figure 6-6 FIFO Write and Read Descriptions (Example shown with Word-Wide Mode)