Word-by-word parity is the easiest mode to implement. In this mode the additional parity bit is sourced to the parity input (PARITYP/N) for each data word transfer into the D[15:0]P/N inputs. This mode is enabled by setting the word_parity_ena bit. The input parity value is defined to be the total number of logic 1s on the 17-bit data bus, the D[15:0]P/N inputs and the PARITYP/N input. This value, the total number of logic 1s, must match the parity test selected in the oddeven_parity bit in register config1.

For example, if the oddeven_parity bit is set to 1b for odd parity, then the number of 1s on the 17-bit data bus should be odd. The DAC checks the data transfer through the parity input. If the data received has odd number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect. The corresponding alarm for parity error is set accordingly.

Note that unless the unused data pins in byte-wide input format are forced to a known value the word-by-word parity is only available for the word-wide input data format.

Figure 6-29 shows the simple XOR structure used to check word parity. Parity is tested independently for data captured on both rising and falling edges of DATACLK (alarm_rparity and alarm_fparity, respectively). Testing on both edges helps in determining a possible setup/hold issue. Both alarms are captured individually in register config5.

Figure 6-29 DAC3482 Word-by-Word Parity Check