7.3.1 Serial Interface

The serial port of the DAC3484 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of DAC3484. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial interface input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 50 shows the serial interface timing diagram for a DAC3484 write operation. SCLK is the serial interface clock input to DAC3484. Serial data enable SDENB is an active low input to DAC3484. SDIO is serial data in. Input data to DAC3484 is clocked on the rising edges of SCLK.

Figure 50. Serial Interface Write Timing Diagram

Figure 51 shows the serial interface timing diagram for a DAC3484 read operation. SCLK is the serial interface clock input to DAC3484. Serial data enable SDENB is an active low input to DAC3484. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC3484 during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from the DAC3484 during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when they will 3-state.

Figure 51. Serial Interface Read Timing Diagram

7.3.2 Data Interface

The DAC3484 has a 16-bit LVDS bus that accepts quad, 16-bit data either in word-wide or dual byte-wide formats. The quad, 16-bit data can be input to the device using either a single-bus, 16-bit interface or a dual-bus, 8-bit interface. The selection between the two modes is done through 16bit_in in the config2 register. The LVDS bus inputs in each mode are shown in Table 2.

Data is sampled by the LVDS double data rate (DDR) clock DATACLK. Setup and hold requirements must be met for proper sampling.

For both input bus modes, a sync signal, either FRAME or SYNC, can sync the FIFO read and/or write pointers. In byte-wide mode the sync source is needed to establish the correct sample boundaries.

The sync signal, either FRAME or SYNC, can be either a pulse or a periodic signal where the sync period corresponds to multiples of 8 samples. FRAME or SYNC is sampled by a rising edge in DATACLK. The pulse-width t_{(FRAME_SYNC)} needs to be at least equal to 1/2 of the DATACLK period.

For both input bus mode, the value in FRAME sampled by the next falling edge in DATACLK can be used as a block parity value. This feature is enabled by setting frame_parity_ena in register config1 to 1b. Refer to Parity Check Test section for more detail

7.3.2.1 Word-Wide Format

The single-bus, 16-bit interface is selected by setting 16bit_in to 1b in the config2 register. In this mode the 16-bit data for channels A, B, C and D is input word-wide interleaved in the form A₀, B₀, C₀, D₀, A1… into the D[15:0]P/N LVDS bus. Data into the DAC3484 is formatted according to the diagram shown in Figure 52 where index 0 is the data LSB and index 15 is the data MSB.

Figure 52. Word-wide Data Transmission Format

7.3.2.2 Byte-Wide Format

The dual-bus, 8-bit interface is selected by setting 16bit_in to 0b in the config2 register. In this mode the 16-bit data for channels A and B is interleaved in the form A₀[15:8], A₀[7:0], B₀[15:8], B₀[7:0], A₁[15:8]… into the D[15:8]P/N LVDS inputs. Similarly data for channels C and D is interleaved into the D[7:0]P/N LVDS inputs. Data into the DAC3484 is formatted according to the diagram shown in Figure 53 where index 0 is the data LSB and index 15 is the data MSB.

Figure 53. Byte-wide Data Transmission Format

7.3.3 Input FIFO

The DAC3484 includes a 4-channel, 16-bits wide, and 8-samples deep input FIFO which acts as an elastic buffer. The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data rate clock such as the ones resulting from clock-to-data variations from the data source.

Figure 54 shows a simplified block diagram of the FIFO. The following sections provide brief overviews of the FIFO, device synchronization, and device clocking. For more details of the topics, please refer to application note SLAA584.

Figure 54. DAC3484 FIFO Block Diagram

Data is written to the device 16-bits at a time on the rising and falling edges of DATACLK. In order to form a complete 64-bit wide sample (16-bit A-data, 16-bit B-data, 16-bit C-data, and 16-bit D-data) two DATACLK periods are required. Each 64-bit wide sample is written into the FIFO at the address indicated by the write pointer. Similarly, data from the FIFO is read by the FIFO Out Clock 64-bits at a time from the address indicated by the read pointer. The FIFO Out Clock is generated internally from the DACCLK signal and its rate is equal to DACCLK/Interpolation. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the next address.

The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in Figure 54. This offset gives optimal margin within the FIFO. The default read pointer location can be set to another value using fifo_offset(2:0) in register config9 (address 4 by default). Under normal conditions data is written-to and read-from the FIFO at the same rate and consequently the write and read pointer gap remains constant. If the FIFO write and read rates are different, the corresponding pointers will be cycling at different speeds which could result in pointer collision. Under this condition the FIFO attempts to read and write data from the same address at the same time which will result in errors and thus must be avoided.

The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either FRAME or SYNC are used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.

Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be set to reset the read pointer as well. In this case, FIFO Out clock will recapture the write pointer sync signal to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of the reset signal, and will create latency variation based on the capture edge of the FIFO Out Clock. Since the reset signal also synchronizes the clock divider circuit for the FIFO Out Clock generation, the latency variation also includes the capture edge of the DACCLK cycle in the clock divider stage. Ultimately, the variation in capture edge of both the FIFO Out Clock and the DACCLK limits the precise control of the output timing latency. The full latency control of the DAC will be difficult and is not recommended in this setup.

To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 or LMK0480x family to provide the DACCLK and OSTR signals to all the DAC3484 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones establishes proper phase relationship.

The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is necessary to have the FRAME, SYNC, and OSTR signals to repeat at multiples of 8 FIFO samples. To disable FIFO reset, set syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000b.

The frequency limitation for FRAME and SYNC signals are the following:

f_sync = f_DATACLK/(n x 16) where n = 1, 2, … for Word-Wide and Byte-Wide Mode

The frequency limitation for the OSTR signal is the following:

f_OSTR = f_DAC/(n x interpolation x 8) where n = 1, 2, …

The frequencies above are at maximum when n = 1. This is when the FRAME, SYNC, or OSTR have a rising edge transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every n × 8 FIFO samples.

Figure 55. FIFO Write and Read Descriptions

7.3.4 FIFO Modes of Operation

The DAC3484 input FIFO can be completely bypassed through registers config0 and config32. The register configuration for each mode is described in Table 3.

7.3.5 Clocking Modes

The DAC3484 has a dual clock setup in which a DAC clock signal is used to clock the DAC cores and internal digital logic and a separate DATA clock is used to clock the input LVDS receivers and FIFO input. The DAC3484 DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL).

In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC clock directly from a high-quality external clock to the DACCLK input. In most applications system clocking can be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.

Figure 56. Top Level Clock Diagram

7.3.5.2 PLL Mode

In this mode the clock at the DACCLK input functions as a reference clock source to the on-chip PLL. The on-chip PLL will then multiply this reference clock to supply a higher frequency DAC sample rate clock. Figure 57 shows the block diagram of the PLL circuit.

Figure 57. PLL Block Diagram

The DAC3484 PLL mode is selected by setting the following:

1. pll_ena bit in register config24 to 1b to route to the PLL clock path.
2. pll_sleep bit in register config26 to 0b to enable the PLL and VCO.

The output frequency of the VCO is designed to be the in the range from 3.3GHz to 4.0GHz. The prescaler value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse tune bits, pll_vco(5:0) in register config26, can adjust the center frequency of the VCO towards the product of the prescaler value and DAC sample rate clock. Figure 58 shows a typical relationship between coarse tune bits and VCO center frequency.

Figure 58. Typical PLL/VCO Lock Range vs Coarse Tuning Bits

Common wireless infrastructure frequencies (614.4 MHz, 737.28 MHz, 1.2288 GHz, ...) are generated from this VCO frequency in conjunction with the pre-scaler setting as shown in Table 4.

Table 4. VCO Operation

VCO FREQUENCY (MHz)	PRE-SCALE DIVIDER	DESIRED DACCLK (MHz)	pll_p(2:0)
3440.64	7	491.52	111
3686.4	6	614.4	110
3686.4	5	737.28	101
3686.4	3	1228.8	011

The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.

Table 5. PFD and CP Operation

DACCLK FREQUENCY (MHz)	M DIVIDER	PDF UPDATE RATE (MHz)	pll_m(7:0)
491.52	4	122.88	00000100
491.52	8	61.44	00001000
491.52	16	30.72	00010000
491.52	32	15.36	00100000

The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N dividers can keep the PFD frequency below 155 MHz for peak operation.

The overall divide ratio inside the loop is the product of the Pre-Scale and M dividers (P * M) and the following guidelines should be followed:

• The overall divide ratio range is from 24 to 480
• When the overall divide ratio is less than 120, the internal loop filter can guarantee a stable loop
• When the overall divide ratio is greater than 120, an external loop filter or double charge pump is required to ensure loop stability

The single- and double-charge-pump current option are selected by setting pll_cp in register config24 to 01b and 11b, respectively. When using the double-charge-pump setting, an external loop filter is not required. If an external filter is required, the following filter should be connected to the LPF pin (A1 for RKD package and D12 for ZAY package):

Figure 59. Recommended External Loop Filter

The PLL generates an internal OSTR signal and does not require the external LVPECL OSTR signal. The OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same as the PFD frequency. Therefore, using PLL with Dual Sync Sources mode would require the PFD frequency to be the pre-defined OSTR frequency. This will allow the FIFO to be synced correctly by the internal OSTR.

7.3.6 FIR Filters

Figure 60 through Figure 63 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3 interpolating filters where f_IN is the input data rate to the FIR filter. Figure 64 to Figure 67 show the composite filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to 0.6 x f_DATA (the input data rate to the device) with <0.001dB of pass-band ripple and >90dB stop-band attenuation.

The DAC3484 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (f_DAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known sin(x)/x or sinc(x) frequency response (Figure 68, red line). The inverse sinc filter response (Figure 68, blue line) has the opposite frequency response from 0 to 0.4 x Fdac, resulting in the combined response (Figure 68, green line). Between 0 to 0.4 x f_DAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03dB error.

The inverse sinc filter has a gain >1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0dB). For example, if the signal input to FIR4 is at 0.25 x f_DAC, the response of FIR4 is 0.9dB, and the signal must be backed off from full scale by 0.9dB to avoid saturation. The gain function in the QMC blocks can be used to reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based on its frequency.

The filter taps for all digital filters are listed in Table 6. Note that the loss of signal amplitude may result in lower SNR due to decrease in signal amplitude.

SPACER

Figure 60. Magnitude Spectrum for FIR0
SPACER

Figure 62. Magnitude Spectrum for FIR2
SPACER

Figure 64. 2x Interpolation Composite Response
SPACER

Figure 66. 8x Interpolation Composite Response
SPACER

Figure 68. Magnitude Spectrum for Inverse Sinc Filter

Figure 61. Magnitude Spectrum for FIR1
SPACER

Figure 63. Magnitude Spectrum for FIR3
SPACER

Figure 65. 4x Interpolation Composite Response
SPACER

Figure 67. 16x Interpolation Composite Response
SPACER

7.3.7 Complex Signal Mixer

The DAC3484 has two paths of complex signal mixer blocks that contain two full complex mixer (FMIX) blocks and power saving coarse mixer (CMIX) blocks. The signal path is shown in Figure 69.

Figure 69. Path of Complex Signal Mixer

7.3.7.1 Full Complex Mixer

The two FMIX blocks operate with independent Numerically Controlled Oscillators (NCOs) and enable flexible frequency placement without imposing additional limitations in the signal bandwidth. The NCOs have 32-bit frequency registers (phaseaddAB(31:0) and phaseaddCD(31:0)) and 16-bit phase registers (phaseoffsetAB(15:0) and phaseoffsetCD(15:0)) that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 70.

Figure 70. NCO Block Diagram

Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is selected by syncsel_NCO(3:0) in config31. The frequency word in the phaseaddAB(31:0) and phaseaddCD(31:0) registers is added to the accumulators every clock cycle, f_DAC. The output frequency of the NCO is:

Equation 1.

With the complex mixer enabled, the two channels in the mixer path are treated as complex vectors of the form I_IN(t) + j Q_IN(t). The complex signal multiplier (shown in Figure 71) will multiply the complex channels with the sine and cosine terms generated by the NCO. The resulting output, I_OUT(t) + j Q_OUT(t), of the complex signal multiplier is:

I_OUT(t) = (I_IN(t)cos(2πf_NCOt + δ) – Q_IN(t)sin(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

Q_OUT(t) = (I_IN(t)sin(2πf_NCOt + δ) + Q_IN(t)cos(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value and mixer_gain is either 0 or 1. δ is given by:

δ = 2π × phase_offsetAB/CD(15:0)/2¹⁶

The mixer_gain option allows the output signals of the multiplier to reduce by half (6dB). See Mixer Gain section for details.

Figure 71. Complex Signal Multiplier

7.3.7.3 Mixer Gain

The maximum output amplitude out of the complex signal multiplier (i.e., FMIX mode or CMIX mode with fs/8 mixer enabled) occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and the sine and cosine arguments are equal to 2π x f_MIXt + δ (2N-1) x π/4, where N = 1, 2, 3, etc....

Figure 72. Maximum Output of the Complex Signal Multiplier

With mixer_gain = 1 and both I_IN(t) and Q_IN(t) are simultaneously full scale amplitude, the maximum output possible out of the complex signal multiplier is 0.707 + 0.707 = 1.414 (or 3dB). This configuration can cause clipping of the signal and should therefore be used with caution.

With mixer_gain = 0 in config2, the maximum output possible out of the complex signal multiplier is 0.5 x (0.707 + 0.707) = 0.707 (or -3dB). This loss in signal power is in most cases undesirable, and it is recommended that the gain function of the QMC block be used to increase the signal by 3dB to compensate.

7.3.8 Quadrature Modulation Correction (QMC)

7.3.8.1 Gain and Phase Correction

The DAC3484 includes a Quadrature Modulator Correction (QMC) block. The QMC blocks provide a mean for changing the gain and phase of the complex signals to compensate for any I and Q imbalances present in an analog quadrature modulator. The block diagram for the QMC block is shown in Figure 73. The QMC block contains 3 programmable parameters.

Register qmc_gainA/B(10:0) and qmc_gainC/D(10:0) controls the I and Q path gains and is an 11-bit unsigned value with a range of 0 to 1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication is between bit 9 and bit 10.

Register qmc_phaseAB/CD(11:0) control the phase imbalance between I and Q and is a 12-bit values with a range of –0.5 to approximately 0.49975. The QMC phase term is not a direct phase rotation but a constant that is multiplied by each "Q" sample then summed into the "I" sample path. This is an approximation of a true phase rotation in order to keep the implementation simple. The corresponding phase rotation corresponds to approximately +26.5 to –26.5 degrees in 4096 steps.

LO feed-through can be minimized by adjusting the DAC offset feature described below.

Figure 73. QMC Block Diagram

7.3.8.2 Offset Correction

Registers qmc_offsetA(12:0), qmc_offsetB(12:0), qmc_offsetC(12:0) and qmc_offsetD(12:0) can be used to independently adjust the DC offsets of each channel. The offset values are in represented in 2s-complement format with a range from -4096 to 4095.

The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset values are LSB aligned.

Figure 74. Digital Offset Block Diagram

7.3.9 Temperature Sensor

The DAC3484 incorporates a temperature sensor block which monitors the temperature by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled (tsense_sleep = 0b in register config26) a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in config6. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from config6 must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

7.3.10 Data Pattern Checker

The DAC3484 incorporates a simple pattern checker test in order to determine errors in the data interface. The main cause of failures is setup/hold timing issues. The test mode is enabled by asserting iotest_ena in register config1. In test mode the analog outputs are deactivated regardless of the state of TXENABLE or sif_texnable in register config3.

The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in registers config37 through config44. The data pattern key can be modified by changing the contents of these registers.

The first word in the test frame is determined by a rising edge transition in FRAME or SYNC, depending on the syncsel_fifoin(4:0) setting in config32. At this transition, the pattern0 word should be input to the data pins. Patterns 1 through 7 should follow sequentially on each edge of DATACLK (rising and falling). The sequence should be repeated until the pattern checker test is disabled by setting iotest_ena back to 0b. It is not necessary to have a rising FRAME or SYNC edge aligned with every pattern0 word, just the first one to mark the beginning of the series.

Figure 75. IO Pattern Checker Data Transmission Format

The test mode determines if the 16-bit LVDS data D[15:0]P/N of all the patterns were received correctly by comparing the received data against the data pattern key. If any of the 16-bit data D[15:0]P/N were received incorrectly, the corresponding bits in iotest_results(15:0) in register config4 will be set to 1b to indicate bit error location. Furthermore, the error condition will trigger the alarm_from_iotest bit in register config5 to indicate a general error in the data interface. When data pattern checker mode is enabled, this alarm in register config5, bit 7 is the only valid alarm. Other alarms in register config5 are not valid and can be disregarded.

For instance, pattern0 is programmed to the default of 0x7A7A. If the received Pattern 0 is 0x7A7B, then bit 0 in iotest_results(15:0) will be set to 1b to indicate an error in bit 0 location. The alarm_from_iotest will also be set to 1b to report the data transfer error. The user can then narrow down the error from the bit location information and implement the fix accordingly.

The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and 0b to alarm_from_iotest through the serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The corresponding alarm bit will remain a 1b if the errors remain.

It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete cycles before clearing the iotest_results(15:0) and alarm_from_iotest. This will eliminate the possibility of false alarms generated during the setup sequence.

Based on the pattern test result, the user can adjust the data source output timing, PCB traces delay, or DAC3484 CONFIG36 LVDS Programmable delay to help optimize the setup and hold time of the transmitter system.

Figure 76. DAC3484 Pattern Check Block Diagram

7.3.11 Parity Check Test

The DAC3484 has a parity check test that enables continuous validity monitoring of the data received by the DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting board assembly issues due to missing pad connections.

For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits (bits with value 1) is even or odd. This simple scheme is used to detect single or any other odd number of data transfer errors. Parity testing is implemented in the DAC3484 in two ways: word-by-word parity and block parity.

7.3.11.1 Word-by-Word Parity

Word-by-word parity is the easiest mode to implement. In this mode the additional parity bit is sourced to the parity input (PARITYP/N) for each data word transfer into the D[15:0]P/N inputs. This mode is enabled by setting the word_parity_ena bit. The input parity value is defined to be the total number of logic 1s on the 17-bit data bus, the D[15:0]P/N inputs and the PARITYP/N input. This value, the total number of logic 1s, must match the parity test selected in the oddeven_parity bit in register config1.

For example, if the oddeven_parity bit is set to 1b for odd parity, then the number of 1s on the 17-bit data bus should be odd. The DAC will check the data transfer through the parity input. If the data received has odd number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect. The corresponding alarm for parity error will be set accordingly.

Figure 77 shows the simple XOR structure used to check word parity. Parity is tested independently for data captured on both rising and falling edges of DATACLK (alarm_rparity and alarm_fparity, respectively). Testing on both edges helps in determining a possible setup/hold issue. Both alarms are captured individually in register config5.

Figure 77. DAC3484 Word-by-Word Parity Check

7.3.11.2 Block Parity

The block parity method uses the FRAME signal to determine the boundaries of the data block to compute parity. This mode is enabled by setting the frame_parity_ena bit in register config1.

A low-to-high transition of FRAME captured with the DATACLK rising edge determines the end point of the parity block and the beginning of the next one. In this method the parity bit of the completed block corresponds to the FRAME value captured on the DATACLK falling edge right after the STOP/START point.

The input parity value is defined to be the total number of logic 1s in the data block. A logic HIGH captured on the falling edge of DATACLK indicates odd parity or odd number of logic 1s, while a logic LOW indicates even parity or even number of logic 1s. If the expected parity does not match the number of logic 1s in the received data, then alarm_frame_parity in register config5 will be set to 1b. The main advantage of the block parity mode is that there is no need for an additional parity LVDS input.

Since the FRAME signal is used for parity testing in addition to FIFO syncing and frame boundary assignment it is mandatory to take some extra steps to avoid device malfunction. If FRAME is used to reset the FIFO pointers continuously, the block size must be a multiple of 8 samples (each sample corresponding to 16-bits A, B, C and D data). In addition since FRAME is used to establish the frame boundary, the parity block must be aligned with the data frame boundaries.

NOTES:

Rising edge of FRAMEP/N indicates the beginning of data block.

Parity bit for the current data block is latched on falling edge of DATACLK after the start point for next data block.

Figure 78. DAC3484 Block Parity Check (Example shown with Word Wide Mode)

7.3.12 DAC3484 Alarm Monitoring

The DAC3484 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. All the alarm events can be accessed either through the config5 register or through the ALARM pin. Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to allow further testing. The set of alarms includes the following conditions:

Zero check alarm

• Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a shift register, all zeros will cause the input pointer to be stuck until the next sync event. When this happens a sync to the FIFO block is required.

FIFO alarms

• alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
  • alarm_fifo_2away. Pointers are within two addresses of each other.
  • alarm_fifo_1away. Pointers are within one address of each other.
  • alarm_fifo_collision. Pointers are equal to each other.

Clock alarms

• clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
  • alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
  • alarm_dataclk_gone. Occurs when the DATACLK has been stopped.

Pattern checker alarm

• alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.

PLL alarm

• alarm_from_pll. Occurs when the PLL is out of lock.

Parity alarms

• alarm_rparity. Occurs when there is a parity error in the data captured by the rising edge of DATACLKP/N. The PARITYP/N input is the parity bit (word-by-word parity test).
• alarm_fparity. Occurs when there is a parity error in the data captured by the falling edge of DATACLKP/N. The PARITYP/N input is the parity bit (word-by-word parity test).
• alarm_frame_parity_err. Occurs when there is a frame parity error when using the FRAME as the parity bit (block parity test).

To prevent unexpected DAC outputs from propagating into the transmit channel chain, the clock and alarm_ fifo_collision alarms can be set in config2 to shut-off the DAC output automatically regardless of the state of TXENABLE or sif_txenable.

Alarm monitoring is implemented as follows:

• Power up the device using the recommended power-up sequence.
• Clear all the alarms in config5 by setting them to 0.
• Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7.
• Enable automatic DAC shut-off in register config2 if required.
• In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the DAC outputs will be disabled.
• Read registers config5 to determine which alarm triggered the ALARM pin.
• Correct the error condition and re-synchronize the FIFO.
• Clear the alarms in config5.
• Re-read config5 to ensure the alarm event has been corrected.
• Keep clearing and reading config5 until no error is reported.

For details of alarm monitoring function and behavior, refer to SLAA585.

7.3.13 LVPECL Inputs

Figure 79 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the output strobe clock (OSTRP/N).

NOTE:

Input common mode level is internally biased

Figure 79. DACCLKP/N and OSTRP/N Equivalent Input Circuit

Figure 80 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential ECL/PECL source.

NOTE:

Actual R_T value depends on differential clock driver output termination recommendation. It is driver type dependent.

Figure 80. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source

7.3.14 LVDS Inputs

The D[15:0]P/N, DATACLKP/N, SYNCP/N, PARITYP/N, and FRAMEP/N LVDS pairs have the input configuration shown in Figure 81. Figure 82 shows the typical input levels and common-move voltage used to drive these inputs.

Figure 81. D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N LVDS Input Configuration

Figure 82. LVDS Data Input Levels

7.3.15 Unused LVDS Port Termination

Depending on the DAC3484 functionality required, additional unused LVDS ports such as FRAMEP/N, SYNCP/N, or PARITYP/N can be left unconnected (floating) or connected to a nominal, differential LVDS active HIGH or active LOW voltage. The usage of these ports depends mainly on the FIFO synchronization settings and parity checking settings. The unused FRAMEP/N, SYNCP/N, or PARITYP/N ports can be connected in parallel with the unused LVDS data port with adjustments to the R_SET resistor value.

The following example allows the termination of the unused LVDS ports to a known logic HIGH value. As shown in Figure 83, The design involves the connection to the DIGVDD rail and one R_SET resistor to bias the positive terminals of unused LVDS ports to be 1.2 V and negative terminals of unused LVDS ports to 1.0 V. The design keeps the minimum common mode input voltage of the LVDS input to be above 1.0 V, and keeps the differential LVDS voltage to be 200 mV. Since the design expects the differential voltage on the unused ports to be static, the differential LVDS voltage can be as low as 100 mV to maintain a logic HIGH. Refer to Electrical Characteristic – Digital Specifications Table for detail of LVDS Input requirements.

Figure 83. Unused LVDS Ports Connected to Static Logic High Differential Voltage

1. Connect the positive terminals of unused LVDS ports in parallel to DIGVDD supply at 1.2 V nominal. For instance, connect SYNC and PARITY positive pins together to DIGVDD.
2. Connect the negative terminals of unused LVDS ports in parallel to a R_SET resistor to ground.
3. The R_EQ value is the equivalent, parallel resistance of the on-chip termination for all the unused LVDS ports. With the SYNC and PARITY ports unused, the R_EQ is two parallel Z_T. Worst case Z_T value of 135 Ω is used in the design to account for the lowest possible current I_EQ and the worst case common mode on the negative LVDS terminals. Another analysis will be performed with Z_T value of 85 Ω for worst case differential LVDS voltages.
4. With Ohm’s Law, the following equation describes the relationship between R_SET and R_EQ.
Equation 2.
5. With R_EQ of two parallel, 135 Ω Z_T (or 67.5 Ω equivalent), R_SET is 332 Ω with standard 1% resistor value. I_EQ is approximately 3 mA. The expected voltage at negative terminals of LVDS ports is approximately 1.0 V. The differential LVDS voltage is 200 mV.
6. With same R_SET of 332 Ω, if the R_EQ has dropped to two parallel, 85 Ω Z_T (or 42.5 Ω equivalent), I_EQ is approximately 3.2 mA. The expected voltage at negative terminals of LVDS port is approximately 1.06 V. The differential LVDS voltage is 136 mV. As long as the static LVDS differential voltage is above 100 mV, the LVDS port will register a logic HIGH value for the data.

7.3.16 CMOS Digital Inputs

Figure 84 shows a schematic of the equivalent CMOS digital inputs of the DAC3484. SDIO, SCLK, SLEEP and TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3484. See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.

Figure 84. CMOS Digital Equivalent Input

7.3.17 Reference Operation

The DAC3484 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor R_BIAS to pin BIASJ. The bias current I_BIAS through resistor R_BIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale output current equals 64 times this bias current and can thus be expressed as:

IOUT_FS = 64 x I_BIAS = 64 x (V_EXTIO / R_BIAS ) / 2

The DAC3484 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the IOUT_FS can be expressed as:

IOUT_FS = (coarse_dac + 1)/16 x I_BIAS x 64 = (coarse_dac + 1)/16 x (V_EXTIO / R_BIAS) / 2 x 64

where V_EXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2 V. This reference is active when extref_ena = 0b in config27. An external decoupling capacitor C_EXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor C_EXT may hence be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor R_BIAS or changing the externally applied reference voltage.

7.3.18 DAC Transfer Function

The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output current up to 30 mA. Differential current switches direct the current to either one of the complementary output nodes IOUTP or IOUTN. Complementary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of two.

The full-scale output current is set using external resistor R_BIAS in combination with an on-chip bandgap voltage reference source (+1.2 V) and control amplifier. Current I_BIAS through resistor R_BIAS is mirrored internally to provide a maximum full-scale output current equal to 64 times I_BIAS.

The relation between IOUTP and IOUTN can be expressed as:

IOUT_FS = IOUTP + IOUTN

We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in each pin driving a resistive load can be expressed as:

IOUTP = IOUT_FS x CODE / 65536

IOUTN = IOUT_FS x (65535 – CODE) / 65536

where CODE is the decimal representation of the DAC data input word

For the case where IOUTP and IOUTN drive resistor loads R_L directly, this translates into single ended voltages at IOUTP and IOUTN:

VOUTP = IOUT1 x R_L

VOUTN = IOUT2 x R_L

Assuming that the data is full scale (65535 in offset binary notation) and the R_L is 25 Ω, the differential voltage between pins IOUTP and IOUTN can be expressed as:

VOUTP = 20mA x 25 Ω = 0.5 V

VOUTN = 0mA x 25 Ω = 0 V

VDIFF = VOUTP – VOUTN = 0.5V

Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would lead to increased signal distortion.

7.3.19 Analog Current Outputs

The DAC3484 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF transformer. Figure 85 and Figure 86 show the 50-Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a DC current flow. Applying a 20-mA full-scale output current would lead to a 0.5 Vpp for a 1:1 transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer results in an output between –0.5 V and 0.5 V.

Figure 85. Driving a Doubly terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer

Figure 86. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer

7.4.1 Multi-Device Synchronization

In various applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase aligned. The DAC3484 architecture supports this mode of operation.

7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode

For single or multi-device synchronization it is important that delay differences in the data are absorbed by the device so that latency through the device remains the same. Furthermore, to guarantee that the outputs from each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In the DAC3484 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode the additional OSTR signal is required by each DAC3484 to be synchronized.

Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into the multiple DAC devices can experience different delays due to variations in the digital source output paths or board level wiring. These different delays can be effectively absorbed by the DAC3484 FIFO so that all outputs are phase aligned correctly.

Figure 87. SynchronizationSystem in Dual Sync Sources Mode with PLL Bypassed

For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.

Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from device to device with the lowest skew possible as this will affect the synchronization process. In order to minimize the skew across devices it is recommended to use the same clock distribution device to provide the DACCLK and OSTR signals to all the DAC devices in the system.

Figure 88. Timing Diagram for LVPECL Synchronization Signals

The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the DAC3484 devices have a DACCLK and OSTR signal and must be carried out on each device.

1. Start-up the device as described in the power-up sequence. Set the DAC3484 in Dual Sync Sources mode and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).
2. Sync the clock divider and FIFO pointers.
3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
4. Disable clock divider sync by setting clkdiv_sync_ena to 0b in register config0.

After these steps all the DAC3484 outputs will be synchronized.

7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode

The DAC3484 allows exact phase alignment between multiple devices even when operating with the internal PLL clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal.

For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state by setting pll_ndivsync_ena in register config24 to 1b. The SYNC signal resets the PLL N dividers with a rising edge, and the timing relationship t_{s(SYNC_PLL)} and t_{h(SYNC_PLL)} are relative to the reference clock presented on the DACCLK pin.

Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the pll_ndivsync_ena bit after resetting the PLL dividers). Besides the t_{s(SYNC_PLL)} and t_{h(SYNC_PLL)} requirement between SYNC and DACCLK, there is no additional required timing relationship between the SYNC and FRAME signals or between DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK and SYNC signals are distributed from device to device with the lowest skew possible.

Figure 89. Synchronization System in Dual Sync Sources Mode with PLL Enabled

The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the DAC3484 devices have a DACCLK and SYNC signal and the following steps must be carried out on each device.

1. Start-up the device as described in the power-up sequence. Set the DAC3484 in Dual Sync Sources mode and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to 1b).
2. Reset the PLL dividers with a rising edge on SYNC.
3. Disable PLL dividers resetting.
4. Sync the clock divider and FIFO pointers.
5. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
6. Disable clock divider sync by setting clkdiv_sync_ena to 0b in register config0.

After these steps all the DAC3484 outputs will be synchronized.

7.4.1.3 Multi-Device Operation: Single Sync Source Mode

In Single Sync Source mode the FIFO read pointer reset is handoff between the two clock domains (DATACLK and FIFO OUT CLOCK) by simply re-sampling the write pointer reset. Since the two clocks are asynchronous there is a small but distinct possibility of a meta-stability during the pointer handoff. As described in the Input FIFO section, this meta-stable situation can change the latency of the multiple DAC devices by both the FIFO Out clock cycles and DAC clock cycles.

When the PLL is enabled with Single Sync Source mode, the FIFO read pointer is not synchronized by the OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section.

Figure 90. Multi-Device Operation in Single Sync Source Mode

7.5.1 Power-Up Sequence

The following startup sequence is recommended to power-up the DAC3484:

1. Set TXENABLE low
2. Supply all 1.2-V voltages (DACVDD, DIGVDD, CLKVDD, and VFUSE) and all 3.3-V voltages (AVDD, IOVDD, and PLLAVDD). The 1.2-V and 3.3-V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after the SIF register programming.
4. Toggle the RESETB pin for a minimum 25 ns active low pulse width.
5. Program the SIF registers.
6. Program fuse_sleep (config27, bit<11>) to put the internal fuses to sleep. To enable dual channel mode, set Config1, bit <8> to 0b and Config16, bit<13:12> to 11b. This dual channel mode is functionally equivalent to the dual channel DAC3484 (channels B and C active). See the DAC3484 SLAS748 datasheet for details.
7. FIFO configuration needed for synchronization:
   1. Program syncsel_fifoin(3:0) (config32, bits<15:12>) to select the FIFO input pointer sync source.
   2. Program syncsel_fifoout(3:0) (config32, bits<11:8>) to select the FIFO output pointer sync source.
   3. Program syncsel_dataformatter(1:0) (config31, bits<3:2>) to select the FIFO Data Formatter sync source.
8. Clock divider configuration needed for synchronization:
   1. Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source.
   2. Program clkdiv_sync_ena (config0, bit<2>) to 1b to enable clock divider sync.
   3. For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit<11>) to 1b to synchronize the PLL N-divider.
9. Provide all LVDS inputs (D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, and PARITYP/N) simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
   1. For Single Sync Source Mode where either FRAMEP/N or SYNCP/N is used to sync the FIFO, a single rising edge for FIFO, FIFO data formatter, and clock divider sync is recommended. Periodic sync signal is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer.
   2. For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.
   3. For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL N-divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as long as the t_{(SYNC_PLL)} setup and hold timing requirement is met with respect to the reference clock source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point.
10. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed for synchronization:
    1. For Single Sync Source Mode where the clock divider sync source is either FRAMEP/N or SYNCP/N, clock divider syncing may be disabled after DAC3484 initialization and before the data transmission by setting clkdiv_sync_ena (config0, bit <2>) to 0b. This is to prevent accidental syncing of the clock divider when sending FRAMEP/N or SYNCP/N pulse to other digital blocks.
    2. For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time.
    3. Optionally, to prevent accidental syncing of the FIFO and FIFO data formatter when sending the FRAMEP/N or SYNCP/N pulse to other digital blocks such as NCO, QMC, etc, disable FIFO syncing by setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000b after the FIFO input and output pointers are initialized. Also Disable the FIFO data formatter by setting syncsel_dataformatter(1:0) to 10b or 11b. If the FIFO and FIFO data formatter sync remain enabled after initialization, the FRAMEP/N or SYNCP/N pulse must occur in ways to not disturb the FIFO operation. Refer to the INPUT FIFO section for detail.
    4. Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit<11>) to 0b.
11. Enable transmit of data by asserting the TXENABLE pin or set sif_txenable to 1b.
12. At any time, if any of the clocks (i.e DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 7 through 11. Program the FIFO configuration and clock divider configuration per steps 7 and 8 appropriately to accept the new sync pulse or pulses for the synchronization.

7.5.2 Example Start-Up Routine

Table 11. Register Map⁽¹⁾

7.6.1 Register Descriptions

Table 15. Register Name: config3 – Address: 0x03, Default: 0xF000

Register Name	Address	Bit	Name	Function	Default Value
config3	0x03	15:12	coarse_dac(3:0)	Scales the output current in 16 equal steps.	1111
		11:8	Reserved	Reserved for factory use.	0000
		7:1	Reserved	Reserved for factory use.	0000000
		0	sif_txenable	When set, the internal value of TXENABLE is set to 1b. To enable analog output data transmission, set sif_txenable to 1b or pull CMOS TXENABLE pin (A32 for DAC3484IRKD and N9 for DAC3484IZAY) to high. To disable analog output, set sif_txenable to 0b and pull CMOS TXENABLE pin (A32 for DAC3484IRKD and N9 for DAC3484IZAY) to low.	0