SLAS751D March   2011  – September 2015 DAC34H84

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements - Digital Specifications
    9. 6.9  Switching Characteristics - AC Specifications
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
      3. 7.3.3  Data Format
      4. 7.3.4  Input FIFO
      5. 7.3.5  FIFO Modes of Operation
        1. 7.3.5.1 Dual Sync Sources Mode
        2. 7.3.5.2 Single Sync Source Mode
        3. 7.3.5.3 Bypass Mode
      6. 7.3.6  Clocking Modes
        1. 7.3.6.1 PLL Bypass Mode
        2. 7.3.6.2 PLL Mode
      7. 7.3.7  FIR Filters
      8. 7.3.8  Complex Signal Mixer
        1. 7.3.8.1 Full Complex Mixer
        2. 7.3.8.2 Coarse Complex Mixer
        3. 7.3.8.3 Mixer Gain
        4. 7.3.8.4 Real Channel Upconversion
      9. 7.3.9  Quadrature Modulation Correction (QMC)
        1. 7.3.9.1 Gain and Phase Correction
        2. 7.3.9.2 Offset Correction
        3. 7.3.9.3 Group Delay Correction
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Data Pattern Checker
      12. 7.3.12 Parity Check Test
        1. 7.3.12.1 32-Bit Parity
        2. 7.3.12.2 Dual 16-Bit Parity
      13. 7.3.13 DAC34H84 Alarm Monitoring
      14. 7.3.14 LVPECL Inputs
      15. 7.3.15 LVDS Inputs
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. 7.5.2.1 Device Configuration
        2. 7.5.2.2 PLL Configuration
        3. 7.5.2.3 NCO Configuration
        4. 7.5.2.4 Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Data Input Rate
          2. 8.2.1.2.2 Interpolation
          3. 8.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Data Input Rate
          2. 8.2.2.2.2 Interpolation
          3. 8.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Assembly
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Definition of Specifications
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

ZAY Package
196-Pin NFBGA
Top View
DAC34H84 P0134-01_LAS751.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVDD D10, E11, F11, G11, H11, J11, K11, L10 I Analog supply voltage. (3.3 V)
ALARM N12 O CMOS output for ALARM condition. The ALARM output functionality is defined through the config7 register. Default polarity is active high, but can be changed to active low via config0 alarm_out_pol control bit.
BIASJ H12 O Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩ to ground. Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>
CLKVDD C12, K12 I Internal clock buffer supply voltage. (1.2 V). It is recommended to isolate this supply from DIGVDD and DACVDD.
DAB[15..0]P A7, A6, A5, A4, A3, A2, A1, C4, C2, D4, D2, E4, E2, F4, F2, G4 I LVDS positive input data bits 0 through 15 for the AB-channel path. Internal 100-Ω termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR).
DAB15P is most significant data bit (MSB)
DAB0P is least significant data bit (LSB)
The order of the bus can be reversed via config2 revbus bit.
DAB[15..0]N B7, B6, B5, B4, B3, B2, B1, C3, C1, D3, D1, E3, E1, F3, F1, G3 I LVDS negative input data bits 0 through 15 for the AB-channel path. (See DAB[15:0]P description above)
DCD[15..0]P H4, J4, J2, K4, K2, L4, L2, M4, M2, N1, N2, N3, N4, N5, N6, N7 I LVDS positive input data bits 0 through 15 for the CD-channel path. Internal 100-Ω termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR).
DCD15P is most significant data bit (MSB)
DCD0P is least significant data bit (LSB)
The order of the bus can be reversed via config2 revbus bit.
DCD[15..0]N H3, J3, J1, K3, K1, L3, L1, M3, M1, P1, P2, P3, P4, P5, P6, P7 I LVDS negative input data bits 0 through 15 for the CD-channel path. (See DCD[15:0]P description above)
DACCLKP A12 I Positive external LVPECL clock input for DAC core with a self-bias.
DACCLKN A11 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)
DACVDD D9, E9, E10, F10, G10, H10, J10, K10, K9, L9 I DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DIGVDD.
DATACLKP G2 I LVDS positive input data clock. Internal 100-Ω termination resistor. Input data DAB[15:0]P/N and DCD[15:0]P/N are latched on both edges of DATACLKP/N (Double Data Rate).
DATACLKN G1 I LVDS negative input data clock. (See DATACLKP description)
DIGVDD E5, E6, E7, F5, J5, K5, K6, K7 I Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD.
EXTIO G12 I/O Used as external reference input when internal reference is disabled through config27 extref_ena = 1b. Used as internal reference output when config27 extref_ena = 0b (default). Requires a 0.1-μF decoupling capacitor to AGND when used as reference output.
ISTRP/
PARITYABP		 H2 I LVDS input strobe positive input. Internal 100-Ω termination resistor.
The main functions of this input are to sync the FIFO pointer, to provide a sync source to the digital blocks, and/or to act as a parity input for the AB-data bus.
These functions are captured with the rising edge of DATACLKP/N. This signal should be edge-aligned with DAB[15:0]P/N and DCD[15:0]P/N.
The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1.
ISTRN/
PARITYABN		 H1 I LVDS input strope negative input. (See the ISTRP/PARITYABP description)
GND A10, A13, A14, B10, B11, B12, B13, C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8, G9, G13, G14, H6, H7, H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14 I These pins are ground for all supplies.
IOUTAP B14 O A-Channel DAC current output. Connect directly to ground if unused.
IOUTAN C14 O A-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTBP F14 O B-Channel DAC current output. Connect directly to ground if unused.
IOUTBN E14 O B-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTCP J14 O C-Channel DAC current output. Connect directly to ground if unused.
IOUTCN K14 O C-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTDP N14 O D-Channel DAC current output. Connect directly to ground if unused.
IOUTDN M14 O D-Channel DAC complementary current output. Connect directly to ground if unused.
IOVDD D5, D6, G5, H5, L5. L6 I Supply voltage for all LVDS I/O. (3.3 V)
IOVDD2 L12 I Supply voltage for all CMOS I/O. (1.8 to 3.3 V) This supply can range from 1.8 V to 3.3 V to change the input and output level of the CMOS I/O.
LPF D12 I/O PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected.
OSTRP A9 I Optional LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in Dual Sync Sources Mode. If unused it can be left unconnected.
OSTRN B9 I Optional LVPECL output strobe negative input. (See the OSTRP description)
PARITYCDP N8 I Optional LVDS positive input parity bit for the CD-data bus. The PARITYCDP/N LVDS pair has an internal 100-Ω termination resistor. If unused it can be left unconnected.
The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1.
PARITYCDN P8 I Optional LVDS negative input parity bit for the CD-data bus.
PLLAVDD C11, D11 I PLL analog supply voltage. (3.3 V)
SCLK P9 I Serial interface clock. Internal pull-down.
SDENB P10 I Active low serial data enable, always an input to the DAC34H84. Internal pull-up.
SDIO P11 1/O Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional 4-pin mode. Internal pull-down.
SDO P12 O Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode (default).
SLEEP N11 I Active high asynchronous hardware power-down input. Internal pull-down.
SYNCP A8 I LVDS SYNC positive input. Internal 100-Ω termination resistor. If unused it can be left unconnected. The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface when setting the rev_interface bit in register config1.
SYNCN B8 I LVDS SYNC negative input.
RESETB N10 I Active low input for chip RESET. Internal pull-up.
TXENA N9 I Transmit enable active high input. Internal pull-down.
To enable analog output data transmission, set sif_txenable in register config3 to 1b or pull CMOS TXENA pin to high.
To disable analog output, set sif_txenable to 0b and pull CMOS TXENA pin to low. The DAC output is forced to midscale.
TESTMODE L11 I This pin is used for factory testing. Internal pull-down. Leave unconnected for normal operation.
VFUSE D7, L7 I Digital supply voltage. This supply pin is also used for factory fuse programming. Connect to DACVDD or DIGVDD for normal operation.
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