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SLAS751D March 2011 – September 2015 DAC34H84

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range⁽²⁾	DACVDD, DIGVDD, CLKVDD	–0.5	1.5	V
	VFUSE	–0.5	1.5	V
	IOVDD, IOVDD2	–0.5	4	V
	AVDD, PLLAVDD	–0.5	4	V
Pin voltage range⁽²⁾	DAB[15..0]P/N, DCD[15..0]P/N, DATACLKP/N, ISTRP/N, PARITYCDP/N, SYNCP/N	–0.5	IOVDD + 0.5	V
	DACCLKP/N, OSTRP/N	–0.5	CLKVDD + 0.5	V
	ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, TXENA	–0.5	IOVDD2 + 0.5	V
	IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N	–1.0	AVDD + 0.5	V
	EXTIO, BIASJ	–0.5	AVDD + 0.5	V
	LPF	–0.5	PLLAVDD + 0.5	V
Peak input current (any input)			20	mA
Peak total input current (all inputs)			–30	mA
Operating free-air temperature range, T_A: DAC34H84		–40	85	°C
Absolute maximum junction temperature, T_J			150	°C
Storage temperature range, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
T_J	Recommended operating junction temperature			105	°C
T_J	Maximum rated operating junction temperature⁽¹⁾	125			°C
T_A	Recommended free-air temperature	–40	25	85	°C

(1) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DAC34H84	UNIT
		ZAY (NFBGA)
		196 BALLS
R_θJA	Junction-to-ambient thermal resistance	37.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	6.8	°C/W
R_θJB	Junction-to-board thermal resistance	16.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	16.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics – DC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUT_FS = 20mA (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Resolution			16			Bits
DC ACCURACY
DNL	Differential nonlinearity	1 LSB = IOUT_FS/2¹⁶		±2		LSB
INL	Integral nonlinearity	1 LSB = IOUT_FS/2¹⁶		±4		LSB
ANALOG OUTPUT
	Coarse gain linearity			±0.04		LSB
	Offset error	Mid code offset		±0.001		%FSR
	Gain error	With external reference		±2		%FSR
	Gain error	With internal reference		±2		%FSR
	Gain mismatch	With internal reference		±2		%FSR
	Full scale output current		10	20	30	mA
	Output compliance range		–0.5		0.6	V
	Output resistance			300		kΩ
	Output capacitance			5		pF
REFERENCE OUTPUT
V_REF	Reference output voltage			1.2		V
	Reference output current⁽²⁾			100		nA
REFERENCE INPUT
V_EXTIO	Input voltage range	External Reference Mode	0.6	1.2	1.25	V
	Input resistance	External Reference Mode		1		MΩ
	Small signal bandwidth			472		kHz
	Input capacitance			100		pF
TEMPERATURE COEFFICIENTS
	Offset drift			±1		ppm/°C
	Gain drift	with external reference		±15		ppm/°C
	Gain drift	with internal reference		±30		ppm/°C
	Reference voltage drift			±8		ppm/°C
POWER SUPPLY⁽³⁾
	AVDD, IOVDD, PLLAVDD		3.14	3.3	3.46	V
	CLKVDD, DACVDD, DIGVDD		1.14	1.2	1.26	V
	IOVDD2		1.71	3.3	3.45	V
PSRR	Power supply rejection ratio	DC tested		±0.25		%FSR/V
POWER CONSUMPTION
I_(AVDD)	Analog supply current⁽⁴⁾	MODE 1⁽⁵⁾ f_DAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL enabled, 20mA FS output, IF = 200MHz		135	165	mA
I_(DIGVDD)	Digital supply current			740	820	mA
I_(DACVDD)	DAC supply current			40	60	mA
I_(CLKVDD)	Clock supply current			100	120	mA
P	Power dissipation			1500	1750	mW
I_(AVDD)	Analog supply current⁽⁴⁾	MODE 2 f_DAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL disabled, 20mA FS output, IF = 200MHz		125		mA
I_(DIGVDD)	Digital supply current			740		mA
I_(DACVDD)	DAC supply current			45		mA
I_(CLKVDD)	Clock supply current			75		mA
P	Power dissipation			1440		mW
I_(AVDD)	Analog supply current⁽⁴⁾	MODE 3 f_DAC = 625MSPS, 2x interpolation, Mixer on, QMC on, invsinc off, PLL disabled, 20mA FS output, IF = 200MHz		120		mA
I_(DIGVDD)	Digital supply current			370		mA
I_(DACVDD)	DAC supply current			25		mA
I_(CLKVDD)	Clock supply current			45		mA
P	Power dissipation			925		mW
I_(AVDD)	Analog supply current⁽⁴⁾	MODE 4 f_DAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL enabled, Channels A/B/C/D output sleep, IF = 200MHz,		50		mA
I_(DIGVDD)	Digital supply current			750		mA
I_(DACVDD)	DAC supply current			40		mA
I_(CLKVDD)	Clock supply current			100		mA
P	Power dissipation			1240		mW
I_(AVDD)	Analog supply current⁽⁴⁾	Mode 5 Power-Down mode: No clock, DAC on sleep mode (clock receiver sleep), Channels A/B/C/D output sleep, static data pattern		40		mA
I_(DIGVDD)	Digital supply current			10		mA
I_(DACVDD)	DAC supply current			5		mA
I_(CLKVDD)	Clock supply current			15		mA
P	Power dissipation			150		mW
I_(AVDD)	Analog supply current⁽⁴⁾	Mode 6 f_DAC = 1GSPS, 2x interpolation, Mixer off, QMC off, invsinc off, PLL enabled, 20mA FS output, IF = 200MHz		140		mA
I_(DIGVDD)	Digital supply current			360		mA
I_(DACVDD)	DAC supply current			30		mA
I_(CLKVDD)	Clock supply current			90		mA
P	Power dissipation			1040		mW
I_(AVDD)	Analog supply current⁽⁴⁾	Mode 7 f_DAC = 1GSPS, 2x interpolation, Mixer off, QMC off, invsinc off, PLL disabled, 20mA FS output, IF = 200MHz		120		mA
I_(DIGVDD)	Digital supply current			370		mA
I_(DACVDD)	DAC supply current			30		mA
I_(CLKVDD)	Clock supply current			65		mA
P	Power dissipation			960		mW

(1) Measured differentially across IOUTP/N with 25 Ω each to GND.

(2) Use an external buffer amplifier with high impedance input to drive any external load.

(3) To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST function in register config27 to check the internal power supply nodes is recommended.

(4) Includes AVDD, PLLAVDD, and IOVDD

(5) PLL operation of 1.25GSPS in Mode 1 is used for maximum power consumption measurement only. Please follow the maximum DAC sample rate (F_DAC) guideline in the AC Characteristic Table for proper DAC operation.

6.6 Electrical Characteristics – Digital Specifications

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N⁽¹⁾
V_A,B+	Logic high differential input voltage threshold		200			mV
V_A,B–	Logic low differential input voltage threshold				–200	mV
V_COM	Input Common Mode		1.0	1.2	1.6	V
Z_T	Internal termination		85	110	135	Ω
C_L	LVDS Input capacitance			2		pF
f_INTERL	Interleaved LVDS data transfer rate				1250	MSPS
f_DATA	Input data rate				625	MSPS
CLOCK INPUT (DACCLKP/N)
	Differential voltage⁽²⁾		0.4	1.0		V
OUTPUT STROBE (OSTRP/N)
	Differential voltage		0.4	1.0		V
CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA
V_IH	High-level input voltage		0.7 x IOVDD2			V
V_IL	Low-level input voltage				0.3 x IOVDD2	V
I_IH	High-level input current		-40		40	µA
I_IL	Low-level input current		-40		40	µA
C_I	CMOS Input capacitance			2		pF
V_OH	ALARM, SDO, SDIO	I_load = –100 μA	IOVDD2 – 0.2			V
V_OH	ALARM, SDO, SDIO	I_load = –2 mA	0.8 x IOVDD2			V
V_OL	ALARM, SDO, SDIO	I_load = 100 μA			0.2	V
V_OL	ALARM, SDO, SDIO	I_load = 2 mA			0.5	V

(1) See LVDS Inputs section for terminology.

(2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance.

6.7 Electrical Characteristics – AC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUT_FS = 20mA (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	UNIT
ANALOG OUTPUT⁽¹⁾
f_DAC	Maximum DAC rate	PLL OFF	1250		MSPS
f_DAC	Maximum DAC rate	PLL ON	1000		MSPS
AC PERFORMANCE⁽²⁾
SFDR	Spurious free dynamic range (0 to f_DAC/2) Tone at 0 dBFS	f_DAC = 1.25 GSPS, f_OUT = 20 MHz		73	dBc
		f_DAC = 1.25 GSPS, f_OUT = 50 MHz		70
		f_DAC = 1.25 GSPS, f_OUT = 70 MHz		66
IMD3	Third-order two-tone intermodulation distortion Each tone at –12 dBFS	f_DAC = 1.25 MSPS, f_OUT = 30 ± 0.5 MHz		87	dBc
		f_DAC = 1.25 GSPS, f_OUT = 50 ± 0.5 MHz		85
		f_DAC = 1.25 GSPS, f_OUT = 100 ± 0.5 MHz		78
NSD	Noise Spectral Density⁽³⁾ Tone at 0dBFS	f_DAC = 1.25 GSPS, f_OUT = 10 MHz		160	dBc/Hz
NSD	Noise Spectral Density⁽³⁾ Tone at 0dBFS	f_DAC = 1.25 GSPS, f_OUT = 80 MHz		155	dBc/Hz
ACLR⁽³⁾	Adjacent channel leakage ratio, single carrier	f_DAC = 1.2288 GSPS, f_OUT = 30.72 MHz		77	dBc
	Adjacent channel leakage ratio, single carrier	f_DAC = 1.2288 GSPS, f_OUT = 153.6 MHz		74
	Alternate channel leakage ratio, single carrier	f_DAC = 1.2288 GSPS, f_OUT = 30.72 MHz		82
	Alternate channel leakage ratio, single carrier	f_DAC = 1.2288 GSPS, f_OUT = 153.6 MHz		80
	Channel Isolation	f_DAC = 1.25 GSPS, f_OUT = 10 MHz		95	dBc

(1) Measured single ended into 50 Ω load.

(2) 4:1 transformer output termination, 50 Ω doubly terminated load

(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms

6.8 Timing Requirements – Digital Specifications

					MIN	NOM	MAX	UNIT
CLOCK INPUT (DACCLKP/N)
	Duty cycle				40%		60%
	DACCLKP/N input frequency						1250	MHz
OUTPUT STROBE (OSTRP/N)
f_OSTR	Frequency	f_OSTR = f_DACCLK / (n x 8 x Interp) where n is any positive integer, f_DACCLK is DACCLK frequency in MHz					f_DACCLK / (8 x interp)	MHz
	Duty cycle					50%
DIGITAL INPUT TIMING SPECIFICATIONS
Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching
t_s(DATA)	Setup time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N and PARITYP/N, valid to either edge of DATACLKP/N	ISTRP/N and SYNCP/N reset latched only on rising edge of DATACLKP/N	Config36 Setting
			datadly	clkdly
			0	0	150			ps
			0	1	100
			0	2	50
			0	3	0
			0	4	-50
			0	5	-100
			0	6	-150
			0	7	-200
			1	0	200
			2	0	250
			3	0	300
			4	0	350
			5	0	400
			6	0	450
			7	0	500
t_h(DATA)	Hold time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N and PARITYP/N, valid after either edge of DATACLKP/N	ISTRP/N and SYNCP/N reset latched only on rising edge of DATACLKP/N	Config36 Setting					ps
			datadly	clkdly
			0	0	400
			0	1	450
			0	2	500
			0	3	550
			0	4	600
			0	5	650
			0	6	700
			0	7	750
			1	0	350
			2	0	300
			3	0	250
			4	0	200
			5	0	150
			6	0	100
			7	0	50
t_{(ISTR_SYNC)}	ISTRP/N and SYNCP/N pulse width	f_DATACLK is DATACLK frequency in MHz			1/2f_DATACLK			ns
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING⁽¹⁾
t_s(OSTR)	Setup time, OSTRP/N valid to rising edge of DACCLKP/N				–100			ps
t_h(OSTR)	Hold time, OSTRP/N valid after rising edge of DACCLKP/N				500			ps
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING⁽²⁾
t_{s(SYNC_PLL)}	Setup time, SYNCP/N valid to rising edge of DACCLKP/N					200		ps
t_{h(SYNC_PLL)}	Hold time, SYNCP/N valid after rising edge of DACCLKP/N					300		ps
TIMING SERIAL PORT
t_s(SDENB)	Setup time, SDENB to rising edge of SCLK				20			ns
t_s(SDIO)	Setup time, SDIO valid to rising edge of SCLK				10			ns
t_h(SDIO)	Hold time, SDIO valid to rising edge of SCLK				5			ns
t_(SCLK)	Period of SCLK	Register config6 read (temperature sensor read)			1			µs
t_(SCLK)	Period of SCLK	All other registers			100			ns
t_d(Data)	Data output delay after falling edge of SCLK					10		ns
t_RESET	Minimum RESETB pulse width					25		ns

(1) OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC34H84 devices in the system. Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship.

(2) SYNC is required to synchronize the PLL circuit in multiple devices. The SYNC signal must meet the timing relationship with respect to the reference clock (DACCLKP/N) of the on-chip PLL circuit.

6.9 Switching Characteristics – AC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUT_FS = 20 mA (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
ANALOG OUTPUT⁽¹⁾
t_s(DAC)	Output settling time to 0.1%	Transition: Code 0x0000 to 0xFFFF	10	ns
t_pd	Output propagation delay	DAC outputs are updated on the falling edge of DAC clock. Does not include Digital Latency (see below).	2	ns
t_r(IOUT)	Output rise time 10% to 90%		220	ps
t_f(IOUT)	Output fall time 90% to 10%		220	ps
	Digital latency	No interpolation, FIFO on, Mixer off, QMC off, Inverse sinc off	128	DAC clock cycles
		2x Interpolation	216
		4x Interpolation	376
		8x Interpolation	726
		16x Interpolation	1427
		Fine mixer	24
		QMC	16
		Inverse sinc	20
Power-up Time	DAC wake-up time	IOUT current settling to 1% of IOUT_FS from output sleep	2	µs
Power-up Time	DAC sleep time	IOUT current settling to less than 1% of IOUT_FS in output sleep	2	µs

(1) Measured single ended into 50-Ω load.

6.10 Typical Characteristics

All plots are at 25°C, nominal supply voltage, f_DAC = 1250 MSPS, 2x interpolation, NCO enabled, Mixer Gain disabled, QMC enabled with gain set at 1446 for both I/Q channels, 0 dBFS digital input, 20 mA full-scale output current with 4:1 transformer (unless otherwise noted)

Figure 1. Integral Nonlinearity

Figure 3. SFDR vs Output Frequency Over Input Scale

Figure 5. Third Harmonic Distortion vs Output Frequency Over Input Scale

Figure 7. SFDR vs Output Frequency Over f_DAC

Figure 9. Single Tone Spectral Plot

Figure 11. Single Tone Spectral Plot

Figure 13. Single Tone Spectral Plot

Figure 15. IMD3 vs Output Frequency Over Interpolation

Figure 17. IMD3 vs Output Frequency Over I_OUTFS

Figure 19. Two Tone Spectral Plot

Figure 21. NSD vs Output Frequency Over Interpolation

Figure 23. NSD vs Output Frequency Over I_OUTFS

Figure 25. Single Carrier WCDMA ACLR (Adjacent) vs Output Frequency Over Clocking Options

Figure 27. Single Carrier W-CDMA Test Model 1

Figure 29. Single Carrier W-CDMA Test Model 1

Figure 31. Four Carrier W-CDMA Test Model 1

Figure 33. 10 MHz Single Carrier LTE Test Model 3.1

Figure 35. 20 MHz Single Carrier LTE Test Model 3.1

Figure 37. Power Consumption vs f_DAC Over Interpolation

Figure 39. Power Consumption vs f_DAC Over Digital Processing Functions

Figure 41. DIGVDD Current vs f_DAC Over Interpolation

Figure 43. DACVDD Current vs f_DAC

Figure 45. AVDD Current vs f_DAC

Figure 47. Channel Isolation vs Output Frequency

Figure 2. Differential Nonlinearity

Figure 4. Second Harmonic Distortion vs Output Frequency Over Input Scale

Figure 6. SFDR vs Output Frequency Over Interpolation

Figure 8. SFDR vs Output Frequency Over I_OUTFS

Figure 10. Single Tone Spectral Plot

Figure 12. Single Tone Spectral Plot

Figure 14. IMD3 vs Output Frequency Over Input Scale

Figure 16. IMD3 vs Output Frequency Over f_DAC

Figure 18. Two Tone Spectral Plot

Figure 20. NSD vs Output Frequency Over Input Scale

Figure 22. NSD vs Output Frequency Over f_DAC

Figure 24. NSD vs Output Frequency Over Clocking Options

Figure 26. Single Carrier WCDMA ACLR (Alternate) vs Output Frequency Over Clocking Options

Figure 28. Single Carrier W-CDMA Test Model 1

Figure 30. Four Carrier W-CDMA Test Model 1

Figure 32. Four Carrier W-CDMA Test Model 1

Figure 34. 10 MHz Single Carrier LTE Test Model 3.1

Figure 36. 20 MHz Single Carrier LTE Test Model 3.1

Figure 38. Power Consumption vs f_DAC Over Interpolation

Figure 40. DIGVDD Current vs f_DAC Over Interpolation

Figure 42. DIGVDD Current vs f_DAC Over Digital Processing Functions

Figure 44. CLKVDD Current vs f_DAC

Figure 46. Channel Isolation vs Output Frequency

Figure 48. Group Delay vs Step Code