ZHCS964E February   2012  – September 2015 DAC34SH84

PRODUCTION DATA.  

1. 1 特性
2. 2 应用范围
3. 3 说明
4. 4 修订历史记录
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Electrical Characteristics - DC Specifications
   6. 6.6  Electrical Characteristics - Digital Specifications
   7. 6.7  Electrical Characteristics - AC Specifications
   8. 6.8  Timing Requirements - Digital Specifications
   9. 6.9  Switching Characteristics - AC Specifications
   10. 6.10 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
      3. 7.3.3  Data Format
      4. 7.3.4  Input FIFO
      5. 7.3.5  FIFO Modes of Operation
         1. 7.3.5.1 Dual-Sync-Sources Mode
         2. 7.3.5.2 Single-Sync-Source Mode
         3. 7.3.5.3 Bypass Mode
      6. 7.3.6  Clocking Modes
         1. 7.3.6.1 PLL Bypass Mode
         2. 7.3.6.2 PLL Mode
      7. 7.3.7  FIR Filters
      8. 7.3.8  Complex Signal Mixer
         1. 7.3.8.1 Full Complex Mixer
         2. 7.3.8.2 Coarse Complex Mixer
         3. 7.3.8.3 Mixer Gain
         4. 7.3.8.4 Real Channel Upconversion
      9. 7.3.9  Quadrature Modulation Correction (QMC)
         1. 7.3.9.1 Gain and Phase Correction
         2. 7.3.9.2 Offset Correction
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Data Pattern Checker
      12. 7.3.12 Parity Check Test
          1. 7.3.12.1 32-Bit Parity
          2. 7.3.12.2 Dual 16-Bit Parity
      13. 7.3.13 DAC34SH84 Alarm Monitoring
      14. 7.3.14 LVPECL Inputs
      15. 7.3.15 LVDS Inputs
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
   4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
         1. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
         2. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
         3. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode
   5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
         1. 7.5.2.1 Device Configuration
         2. 7.5.2.2 PLL Configuration
         3. 7.5.2.3 NCO Configuration
         4. 7.5.2.4 Example Start-Up Sequence
   6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
         1. 8.2.1.1 Design Requirements
         2. 8.2.1.2 Detailed Design Procedure
            1. 8.2.1.2.1 Data Input Rate
            2. 8.2.1.2.2 Interpolation
            3. 8.2.1.2.3 LO Feedthrough and Sideband Correction
         3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
         1. 8.2.2.1 Design Requirements
         2. 8.2.2.2 Detailed Design Procedure
            1. 8.2.2.2.1 Data Input Rate
            2. 8.2.2.2.2 Interpolation
            3. 8.2.2.2.3 LO Feedthrough and Sideband Correction
         3. 8.2.2.3 Application Curves
9. 9 Power Supply Recommendations
10. 10Layout
    1. 10.1 Layout Guidelines
       1. 10.1.1 Assembly
    2. 10.2 Layout Examples
11. 11器件和文档支持
    1. 11.1 器件支持
       1. 11.1.1 Third-Party Products Disclaimer
       2. 11.1.2 器件命名规则
          1. 11.1.2.1 技术参数定义
    2. 11.2 文档支持
       1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
12. 12机械、封装和可订购信息