7.3.1 Serial Interface

The serial port of the DAC34SH84 is a flexible serial interface which communicates with industry-standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of the DAC34SH84. It is compatible with most synchronous transfer formats and can be configured as a three- or four-pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial-interface input clock and SDENB is serial-interface enable. For the three-pin configuration, SDIO is a bidirectional pin for both data in and data out. For the four-pin configuration, SDIO is data-in only and SDO is data-out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by the serial-data enable bar (SDENB) signal asserted low. The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 49 shows the serial interface timing diagram for a DAC34SH84 write operation. SCLK is the serial interface clock input to DAC34SH84. Serial data enable SDENB is an active low input to DAC34SH84. SDIO is serial data in. Input data to DAC34SH84 is clocked on the rising edges of SCLK.

Figure 49. Serial-Interface Write Timing Diagram

Figure 50 shows the serial interface timing diagram for a DAC34SH84 read operation. SCLK is the serial interface clock input to the DAC34SH84. Serial-data enable SDENB is an active-low input to the DAC34SH84. SDIO is serial data-in during the instruction cycle. In the three-pin configuration, SDIO is data out from the DAC34SH84 during the data transfer cycle, whereas SDO is in a high-impedance state. In the four-pin configuration, SDO is data-out from the DAC34SH84 during the data transfer cycle. At the end of the data transfer, SDIO and SDO output low on the final falling edge of SCLK until the rising edge of SDENB, when SDO goes into the high-impedance state.

Figure 50. Serial-Interface Read Timing Diagram

7.3.2 Data Interface

The DAC34SH84 has a 32-bit LVDS bus that accepts quad, 16-bit data in word-wide format. The quad, 16-bit data can be input to the device using a dual-bus, 16-bit interface. The bus accepts LVDS transfer rates up to 1.5 GSPS, which corresponds to a maximum data rate of 750 MSPS per data channel. The default LVDS bus input assignment is shown in Table 2.

Data is sampled by the LVDS double-data-rate (DDR) clock DATACLK. Setup and hold requirements must be met for proper sampling. A and C data are captured on the rising edge of DATACLK. B and D data are captured on the falling edge of DATACLK.

For both input bus modes, a sync signal, either ISTR or SYNC, is required to sync the FIFO read and/or write pointers.

The sync signal, either ISTR or SYNC, can be either a pulse or a periodic signal where the sync period corresponds to multiples of eight samples. ISTR or SYNC is sampled by a rising edge in DATACLK. The pulse duration t_{(ISTR_SYNC)} must be at least equal to one-half of the DATACLK period.

7.3.3 Data Format

The 16-bit data for channels A and B is interleaved in the form A₀[15:0], B₀[15:0], A₁[15:0], B₁[15:0], A₂[15:0]… into the DAB[15:0]P/N LVDS inputs. Similarly, data for channels C and D is interleaved into the DCD[15:0]P/N LVDS inputs. Data into the DAC34SH84 is formatted according to the diagram shown in Figure 51, where index 0 is the data LSB and index 15 is the data MSB.

Figure 51. Data Transmission Format

The FIFO read and write pointer can also be synced by SIF SYNC as the third sync option if multi-device synchronization is not needed. In this sync mode, the syncsel_fifoin(3:0) and syncsel_fifoout(3:0) in register config32 need to be both set to 1000 for the SIF SYNC option.

7.3.4 Input FIFO

The DAC34SH84 includes a 4-channel, 16-bit-wide and 8-sample-deep input FIFO which acts as an elastic buffer. The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data-rate clock, such as the ones resulting from clock-to-data variations from the data source.

Figure 52 shows a simplified block diagram of the FIFO.

Figure 52. DAC34SH84 FIFO Block Diagram

Data is written to the device 32 bits at a time on the rising and falling edges of DATACLK. In order to form a complete 64-bit wide sample (16-bit A-data, 16-bit B-data, 16-bit C-data, and 16-bit D-data) one DATACLK period is required. Each 64-bit-wide sample is written into the FIFO at the address indicated by the write pointer. Similarly, data from the FIFO is read by the FIFO-out clock 64 bits at a time from the address indicated by the read pointer. The FIFO-out clock is generated internally from the DACCLK signal and its rate is equal to DACCLK / interpolation. Each time a FIFO write or FIFO read is done, the corresponding pointer moves to the next address.

The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in Figure 52. This offset gives optimal margin within the FIFO. The default read pointer location can be set to another value using fifo_offset(2:0) in register config9 (address 4 by default). Under normal conditions, data is written to and read from the FIFO at the same rate and consequently, the write and read pointer gap remains constant. If the FIFO write and read rates are different, the corresponding pointers cycle at different speeds, which could result in pointer collision. Under this condition, the FIFO attempts to read and write data from the same address at the same time, which results in errors and thus must be avoided.

The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either ISTR or SYNC are used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.

Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be set to reset the read pointer as well. In this case, the FIFO-out clock recaptures the write pointer sync signal to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of the sync signal. This limits the precise control of the output timing and makes full synchronization of multiple devices difficult.

To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the DAC34SH84 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones establishes proper phase relationship.

The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is necessary to have the ISTR, SYNC, and OSTR signals to repeat at multiples of 8 FIFO samples. To disable FIFO reset, set syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000.

The frequency limitation for ISTR and SYNC signals are the following:

f_sync = f_DATACLK / (n × 8), where n = 1, 2, …

The frequency limitation for the OSTR signal is the following:

f_OSTR = f_DAC / (n × interpolation × 8) where n = 1, 2, …

The frequencies above are at maximum when n = 1. This is when the ISTR, SYNC, or OSTR have a rising edge transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every n × 8 FIFO samples.

Figure 53. FIFO Write and Read Descriptions

7.3.5 FIFO Modes of Operation

The DAC34SH84 input FIFO can be completely bypassed through registers config0 and config32. The register configuration for each mode is described in Table 3.

7.3.6 Clocking Modes

The DAC34SH84 has a dual-clock setup in which a DAC clock signal is used to clock the DAC cores and internal digital logic, and a separate DATA clock is used to clock the input LVDS receivers and FIFO input. The DAC34SH84 DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL).

In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC clock directly from a high-quality external clock to the DACCLK input. In most applications, system clocking can be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance requirements. In this case, the DACCLK pins are used as the reference frequency input to the PLL.

Figure 54. Top-Level Clock Diagram

7.3.6.2 PLL Mode

In this mode, the clock at the DACCLKP/N input functions as a reference clock source to the on-chip PLL. The on-chip PLL then multiplies this reference clock to supply a higher-frequency DAC sample-rate clock. Figure 55 shows the block diagram of the PLL circuit.

Figure 55. PLL Block Diagram

The DAC34SH84 PLL mode is selected by setting the following:

1. pll_ena bit in register config24 to 1 to route to the PLL clock path.
2. pll_sleep bit in register config26 to 0 to enable the PLL and VCO.

The output frequency of the VCO is designed to be the in the range from 2.7 GHz to 3.3 GHz. The prescaler value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse-tuning bits, pll_vco(5:0) in register config26, can adjust the center frequency of the VCO toward the product of the prescaler value and DAC sample-rate clock. Figure 56 shows a typical relationship between the coarse-tuning bits and VCO center frequency. See the Electrical Characteristics Table for recommended pll_vco(5:0) setting and the corresponding VCO frequency range. Following the recommended settings ensures optimal PLL lock range over operating temperature and voltage specifications.

Figure 56. Typical PLL/VCO Lock Range vs Coarse-Tuning Bits

Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 983.04 MHz, and so forth) are generated from this VCO frequency in conjunction with the prescaler setting as shown in Table 4.

Table 4. VCO Operation

VCO FREQUENCY (MHz)	PRE-SCALE DIVIDER	DESIRED DACCLK (MHz)	pll_p(2:0)
2949.12	6	491.52	110
3072	5	614.4	101
2949.12	4	737.28	100
2949.12	3	983.04	011
2949.12	2	1474.56	010

The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.

Table 5. PFD and CP Operation

DACCLK FREQUENCY (MHz)	M DIVIDER	PFD UPDATE RATE (MHz)	pll_m(7:0)
491.52	4	122.88	0000 0100
491.52	8	61.44	0000 1000
491.52	16	30.72	0001 0000
491.52	32	15.36	0010 0000

The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N dividers can keep the PFD frequency below 155 MHz for peak operation.

The overall divide ratio inside the loop is the product of the pre-scale and M dividers (P × M), and the following guidelines should be followed:

• The overall divide ratio range is from 24 to 480.
• When the overall divide ratio is less than 120, the internal loop filter can assure a stable loop.
• When the overall divide ratio is greater than 120, an external loop filter or double charge pump is required to ensure loop stability.

The single- and double-charge-pump current options are selected by setting pll_cp in register config24 to 01 and 11, respectively. When using the double-charge-pump setting, an external loop filter is not required. If an external loop filter is required, the following filter should be connected to the LPF pin (A1):

Figure 57. Recommended External Loop Filter

The PLL generates an internal OSTR signal and does not require the external LVPECL OSTR signal. The OSTR signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same as the PFD frequency. Therefore, using the PLL with dual-sync-sources mode would require the PFD frequency to be the pre-defined OSTR frequency. This allows the FIFO to be synced correctly by the internal OSTR.

7.3.7 FIR Filters

Figure 58 through Figure 61 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3 interpolating filters where f_IN is the input data rate to the FIR filter. Figure 62 to Figure 65 show the composite filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to 0.6 x f_DATA (the input data rate to the device) with < 0.001dB of pass-band ripple and > 90 dB stop-band attenuation.

The DAC34SH84 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (f_DAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known sin(x) / x or sinc(x) frequency response (Figure 66, red line). The inverse sinc filter response (Figure 66, blue line) has the opposite frequency response from 0 to 0.4 x Fdac, resulting in the combined response (Figure 66, green line). Between 0 to 0.4 x f_DAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03 dB error.

The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 dB). For example, if the signal input to FIR4 is at 0.25 x f_DAC, the response of FIR4 is 0.9 dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The gain function in the QMC blocks can be used to reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based on its frequency.

The filter taps for all digital filters are listed in Table 3. Note that the loss of signal amplitude may result in lower SNR due to decrease in signal amplitude.

Figure 58. Magnitude Spectrum for FIR0

Figure 60. Magnitude Spectrum for FIR2

Figure 62. 2x Interpolation Composite Response

Figure 64. 8x Interpolation Composite Response

Figure 66. Magnitude Spectrum for Inverse Sinc Filter

Figure 59. Magnitude Spectrum for FIR1

Figure 61. Magnitude Spectrum for FIR3

Figure 63. 4x Interpolation Composite Response

Figure 65. 16x Interpolation Composite Response

7.3.8 Complex Signal Mixer

The DAC34SH84 has two paths of complex signal mixer blocks that contain two full complex mixer (FMIX) blocks and power saving coarse mixer (CMIX) blocks. The signal path is shown in Figure 67.

NOTE:

Channel CD data path not shown

Figure 67. Path of Complex Signal Mixer

7.3.8.1 Full Complex Mixer

The two FMIX blocks operate with independent Numerically Controlled Oscillators (NCOs) and enable flexible frequency placement without imposing additional limitations in the signal bandwidth. The NCOs have 32-bit frequency registers (phaseaddAB(31:0) and phaseaddCD(31:0)) and 16-bit phase registers (phaseoffsetAB(15:0) and phaseoffsetCD(15:0)) that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 68.

Figure 68. NCO Block Diagram

Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is selected by syncsel_NCO(3:0) in config31. The frequency word in the phaseaddAB(31:0) and phaseaddCD(31:0) registers is added to the accumulators every clock cycle, f_DAC. The output frequency of the NCO is:

Equation 1.

With the complex mixer enabled, the two channels in the mixer path are treated as complex vectors of the form I_IN(t) + j Q_IN(t). The complex signal multiplier (shown in Figure 69) will multiply the complex channels with the sine and cosine terms generated by the NCO. The resulting output, I_OUT(t) + j Q_OUT(t), of the complex signal multiplier is:

I_OUT(t) = (I_IN(t)cos(2πf_NCOt + δ) – Q_IN(t)sin(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

Q_OUT(t) = (I_IN(t)sin(2πf_NCOt + δ) + Q_IN(t)cos(2πf_NCOt + δ)) × 2^{(mixer_gain – 1)}

where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value and mixer_gain is either 0 or 1. δ is given by:

δ = 2π × phase_offsetAB/CD(15:0) / 2¹⁶

The mixer_gain option allows the output signals of the multiplier to reduce by half (6 dB). See Mixer Gain section for details.

Figure 69. Complex Signal Multiplier

7.3.8.3 Mixer Gain

The maximum output amplitude out of the complex signal multiplier (for example, FMIX mode or CMIX mode with f_S / 8 mixer enabled) occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and the sine and cosine arguments are equal to 2π x f_MIXt + δ (2N-1) x π / 4, where N = 1, 2, 3, ...

Figure 70. Maximum Output of the Complex Signal Multiplier

With mixer_gain = 1 and both I_IN(t) and Q_IN(t) are simultaneously full scale amplitude, the maximum output possible out of the complex signal multiplier is 0.707 + 0.707 = 1.414 (or 3dB). This configuration can cause clipping of the signal and should therefore be used with caution.

With mixer_gain = 0 in config2, the maximum output possible out of the complex signal multiplier is 0.5 × (0.707 + 0.707) = 0.707 (or –3 dB). This loss in signal power is in most cases undesirable, and it is recommended that the gain function of the QMC block be used to increase the signal by 3 dB to compensate.

7.3.9 Quadrature Modulation Correction (QMC)

7.3.9.1 Gain and Phase Correction

The DAC34SH84 includes a Quadrature Modulator Correction (QMC) block. The QMC blocks provide a mean for changing the gain and phase of the complex signals to compensate for any I and Q imbalances present in an analog quadrature modulator. The block diagram for the QMC block is shown in Figure 71. The QMC block contains 3 programmable parameters.

Registers qmc_gainA/B(10:0) and qmc_gainC/D(10:0) controls the I and Q path gains and is an 11-bit unsigned value with a range of 0 to 1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication is between bit 9 and bit 10.

Register qmc_phaseAB/CD(11:0) control the phase imbalance between I and Q and are a 12-bit values with a range of –0.5 to approximately 0.49975. The QMC phase term is not a direct phase rotation but a constant that is multiplied by each Q sample then summed into the I sample path. This is an approximation of a true phase rotation in order to keep the implementation simple.

LO feed-through can be minimized by adjusting the DAC offset feature described below.

Figure 71. QMC Block Diagram

7.3.9.2 Offset Correction

Registers qmc_offsetA(12:0), qmc_offsetB(12:0), qmc_offsetC(12:0) and qmc_offsetD(12:0) can be used to independently adjust the dc offsets of each channel. The offset values are in represented in 2s-complement format with a range from –4096 to 4095.

The offset value adds a digital offset to the digital data before digital-to-analog conversion. Because the offset is added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset values are LSB aligned.

Figure 72. Digital Offset Block Diagram

7.3.10 Temperature Sensor

The DAC34SH84 incorporates a temperature sensor block which monitors the temperature by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted as a 2s-complement value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled (tsense_sleep = 0 in register config26) a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in tempdata(7:0) in config6. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from config6 must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

7.3.11 Data Pattern Checker

The DAC34SH84 incorporates a simple pattern checker test in order to determine errors in the data interface. The main cause of failures is setup and/or hold timing issues. The test mode is enabled by asserting iotest_ena in register config1. In test mode the analog outputs are deactivated regardless of the state of TXENA or sif_texnable in register config3.

The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in registers config37 through config44. The data pattern key can be modified by changing the contents of these registers.

The first word in the test frame is determined by a rising edge transition in ISTR or SYNC, depending on the syncsel_fifoin(3:0) setting in config32. At this transition, the pattern0 word should be input to the data DAB[15:0] pins, and pattern2 should be input to the data DCD[15:0] pins. Patterns 1, 4, and 5 of DAB[15:0] bus and pattern 3, 6, and 7 of DCD[15:0] bus should follow sequentially on each edge of DATACLK (rising and falling). The sequence should be repeated until the pattern checker test is disabled by setting iotest_ena back to 0. It is not necessary to have a rising ISTR or SYNC edge aligned with every four DATACLK cycle, just the first one to mark the beginning of the series.

Figure 73. I/O Pattern Checker Data Transmission Format

The test mode determines if the all the patterns on the two 16-bit LVDS data buses (DAB[15:0]P/N and DCD[15:0]P/N) were received correctly by comparing the received data against the data pattern key. If any bits in either of the two 16-bit data buses were received incorrectly, the corresponding bits in iotest_results(15:0) in register config4 will be set to 1 to indicate bit error location. The user can check the corresponding bit location on both 16-bit data buses and implement the fix accordingly. Furthermore, the error condition will trigger the alarm_from_iotest bit in register config5 to indicate a general error in the data interface. When data pattern checker mode is enabled, this alarm in register config5, bit7 is the only valid alarm. Other alarms in register config5 are not valid and can be disregarded.

For instance, pattern0 is programmed to the default of 0x7A7A. If the received Pattern 0 is 0x7A7B, then bit 0 in iotest_results(15:0) will be set to 1 to indicate an error in bit 0 location. The alarm_from_iotest will also be set to 1 to report the data transfer error. Note that iotest_results(15:0) does not indicate which of the 16-bit buses has the error. The user needs to check both 16-bit buses and then narrow down the error from the bit location information.

The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and 0 to alarm_from_iotest through the serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The corresponding alarm bit will remain a 1 if the errors remain.

It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete cycles before clearing the iotest_results(15:0) and alarm_from_iotest. This will eliminate the possibility of false alarms generated during the setup sequence. Based on the pattern test result, the user can adjust the data source output timing, PCB traces delay, or DAC34SH84 CONFIG36 LVDS programmable delay to help optimize the setup and hold time of the transmitter system.

Figure 74. DAC34SH84 Pattern Check Block Diagram

7.3.12 Parity Check Test

The DAC34SH84 has a parity check test that enables continuous validity monitoring of the data received by the DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting board assembly issues due to missing pad connections.

For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits (bits with value 1) is even or odd. This simple scheme is used to detect single or any other odd number of data transfer errors. Parity testing is implemented in the DAC34SH84 in two ways: 32-bit parity and dual 16-bit parity.

7.3.12.1 32-Bit Parity

In the 32-bit mode the additional parity bit is sourced to the parity input (PARITYP/N) for the 32-bit data transfer into the DAB[15:0]P/N and DCD[15:0]P/N inputs. This mode is enabled by setting parity_ena = 1 and single_dual_parity = 0 in register config1. The input parity value is defined to be the total number of logic 1s on the 33-bit data bus – the DAB[15:0]P/N inputs, the DCD[15:0]P/N inputs, and the PARITYP/N input. This value, the total number of logic 1s, must match the parity test selected in the oddeven_parity bit in register config1.

For example, if the oddeven_parity bit is set to 1 for odd parity, then the number of 1s on the 33-bit data bus should be odd. The DAC will check the data transfer through the parity input. If the data received has odd number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect. The corresponding alarm for parity error will be set accordingly.

Figure 75 shows the simple XOR structure used to check word parity. Parity is tested independently for data captured on both rising and falling edges of DATACLK (alarm_Aparity and alarm_Bparity, respectively). Testing on both edges helps in determining a possible setup or hold issue. Both alarms are captured individually in register config5.

Figure 75. DAC34SH84 32-Bit Parity Check

7.3.12.2 Dual 16-Bit Parity

In the dual 16-bit mode, each 16-bit LVDS data bus input will be accompanied by a parity bit for error checking. The DAB[15:0]P/N and ISTRP/N are one 17-bit data path, and the DCD[15:0]P/N and PARITYP/N are another path. This mode is enabled by setting parity_ena = 1 and single_dual_parity = 1 in register config1. The input parity value is defined to be the total number of logic 1s on each 17-bit data bus. This value, the total number of logic 1s, must match the parity test selected in the oddeven_parity bit in register config1.

For example, if the oddeven_parity bit is set to 1 for odd parity, then the number of 1s on each 17-bit data bus should be odd. The DAC will check the data transfer through the parity input. If the data received has odd number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect. The corresponding alarm for parity error will be set accordingly.

Figure 76 shows the simple XOR structure used to check word parity. Parity is tested independently for data captured on both rising and falling edges of DATACLK for each data path (alarm_Aparity, alarm_Bparity, alarm_Cparity, and alarm_Dparity, respectively). Testing on both edges and both data buses helps in determining a possible setup or hold issue. All of the alarms are captured individually in register config5.

In this mode the ISTR signal functions as a parity signal and cannot be used to sync the FIFO pointer simultaneously. It is recommended to use the SYNC to sync the FIFO pointer. If ISTR has to be used to sync the FIFO pointer, the ISTR sync can only be possible upon start-up when dual 16-bit parity function is disabled. Once the initialization is finished, disable the FIFO pointer sync through ISTR (by configuring syncsel_fifoin and syncsel_fifoout in config32) and enable the dual 16-bit parity function afterwards.

Figure 76. DAC34SH84 Dual 16-Bit Parity Check

7.3.13 DAC34SH84 Alarm Monitoring

The DAC34SH84 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. All the alarm events can be accessed either through the config5 register or through the ALARM pin. Once an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface to allow further testing. The set of alarms includes the following conditions:

Zero check alarm

• Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a sync to the FIFO block is required.

FIFO alarms

• alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
  • alarm_fifo_2away. Pointers are within two addresses of each other.
  • alarm_fifo_1away. Pointers are within one address of each other.
  • alarm_fifo_collision. Pointers are equal to each other.

Clock alarms

• clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
  • alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
  • alarm_dataclk_gone. Occurs when the DATACLK has been stopped.

Pattern checker alarm

• alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.

PLL alarm

• alarm_from_pll. Occurs when the PLL is out of lock.

Parity alarms

• alarm_Aparity: In dual parity mode, alarm indicating a parity error on the A word. In single parity mode, alarm on the 32-bit data captured on the rising edge of DATACLKP/N.
• alarm_Bparity: In dual parity mode, alarm indicating a parity error on the B word. In single parity mode, alarm on the 32-bit data captured on the falling edge of DATACLKP/N.
• alarm_Cparity: In dual parity mode, alarm indicating a parity error on the C word.
• alarm_Dparity: In dual parity mode, alarm indicating a parity error on the D word.

To prevent unexpected DAC outputs from propagating into the transmit channel chain, the clock and alarm_ fifo_collision alarms can be set in config2 to shut-off the DAC output automatically regardless of the state of TXENA or sif_txenable.

Alarm monitoring is implemented as follows:

• Power up the device using the recommended power-up sequence.
• Clear all the alarms in config5 by setting them to zeros.
• Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7.
• Enable automatic DAC shut-off in register config2 if required.
• In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the DAC outputs will be disabled.
• Read registers config5 to determine which alarm triggered the ALARM pin.
• Correct the error condition and re-synchronize the FIFO.
• Clear the alarms in config5.
• Re-read config5 to ensure the alarm event has been corrected.
• Keep clearing and reading config5 until no error is reported.

7.3.14 LVPECL Inputs

Figure 77 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the output strobe clock (OSTRP/N).

Figure 77. DACCLKP/N and OSTRP/N Equivalent Input Circuit

Figure 78 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential ECL or PECL source.

Figure 78. Preferred Clock Input Configuration With a Differential ECL or PECL Clock Source

7.3.15 LVDS Inputs

The DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, SYNCP/N, PARITYP/N, and ISTRP/N LVDS pairs have the input configuration shown in Figure 79. Figure 80 shows the typical input levels and common-move voltage used to drive these inputs.

Figure 79. DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N and PARITYP/N LVDS Input Configuration

Figure 80. LVDS Data Input Levels

7.3.16 CMOS Digital Inputs

Figure 81 shows a schematic of the equivalent CMOS digital inputs of the DAC34SH84. SDIO, SCLK, SLEEP and TXENA have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC34SH84. All the CMOS digital inputs and outputs are referred to the IOVDD2 supply, which can vary from 1.8 V to 3.3 V. This facilitates the I/O interface and eliminates the need of level translation. See Electrical Characteristics – Digital Specifications for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100 kΩ.

Figure 81. CMOS Digital Equivalent Input

7.3.17 Reference Operation

The DAC34SH84 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor R_BIAS to pin BIASJ. The bias current I_BIAS through resistor R_BIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale output current equals 64 times this bias current and can thus be expressed as:

IOUT_FS = 64 × I_BIAS = 64 × (V_EXTIO / R_BIAS ) / 2

The DAC34SH84 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the IOUT_FS can be expressed as:

IOUT_FS = (coarse_dac + 1) / 16 × I_BIAS × 64 = (coarse_dac + 1) / 16 × (VEXTIO / RBIAS) / 2 × 64

where V_EXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2 V. This reference is active when extref_ena = 0 in config27. An external decoupling capacitor C_EXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor C_EXT may hence be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor R_BIAS, programming coarse_dac(3:0), or changing the externally applied reference voltage.

7.3.18 DAC Transfer Function

The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output current up to 30 mA. Differential current switches direct the current to either one of the complementary output nodes IOUTP or IOUTN. Complementary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of two.

The full-scale output current is set using external resistor R_BIAS in combination with an on-chip bandgap voltage reference source (+1.2 V) and control amplifier. Current I_BIAS through resistor R_BIAS is mirrored internally to provide a maximum full-scale output current equal to 64 times I_BIAS.

The relation between IOUTP and IOUTN can be expressed as:

IOUT_FS = IOUTP + IOUTN

We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in each pin driving a resistive load can be expressed as:

IOUTP = IOUT_FS × CODE / 65,536

IOUTN = IOUT_FS × (65,535 – CODE) / 65,536

where CODE is the decimal representation of the DAC data input word

For the case where IOUTP and IOUTN drive resistor loads R_L directly, this translates into single ended voltages at IOUTP and IOUTN:

VOUTP = IOUT1 x R_L

VOUTN = IOUT2 x R_L

Assuming that the data is full scale (65,535 in offset binary notation) and the R_L is 25 Ω, the differential voltage between pins IOUTP and IOUTN can be expressed as:

VOUTP = 20mA x 25 Ω = 0.5 V

VOUTN = 0mA x 25 Ω = 0 V

VDIFF = VOUTP – VOUTN = 0.5V

Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would lead to increased signal distortion.

7.3.19 Analog Current Outputs

The DAC34SH84 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF transformer. Figure 82 and Figure 83 show the 50-Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a DC current flow. Applying a 20-mA full-scale output current would lead to a 0.5 Vpp for a 1:1 transformer and a 1-Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer results in an output between –0.5 V and +0.5 V.

Figure 82. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer

Figure 83. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer

7.4.1 Multi-Device Synchronization

In various applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase aligned. The DAC34SH84 architecture supports this mode of operation.

7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode

For single- or multi-device synchronization it is important that delay differences in the data are absorbed by the device so that latency through the device remains the same. Furthermore, to ensure that the outputs from each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In the DAC34SH84 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode the additional OSTR signal is required by each DAC34SH84 to be synchronized.

Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into multiple DAC devices can experience different delays due to variations in the digital source output paths or board level wiring. These different delays can be effectively absorbed by the DAC34SH84 FIFO so that all outputs are phase aligned correctly.

Figure 84. Synchronization System in Dual Sync Sources Mode With PLL Bypassed

For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.

Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from device to device with the lowest skew possible as this will affect the synchronization process. In order to minimize the skew across devices it is recommended to use the same clock distribution device to provide the DACCLK and OSTR signals to all the DAC devices in the system.

Figure 85. Timing Diagram for LVPECL Synchronization Signals

The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the DAC34SH84 devices have a DACCLK and OSTR signal and must be carried out on each device.

1. Start-up the device as described in the power-up sequence. Set the DAC34SH84 in Dual Sync Sources mode and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).
2. Sync the clock divider and FIFO pointers.
3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
4. Disable clock divider sync by setting clkdiv_sync_ena to 0 in register config0.

After these steps all the DAC34SH84 outputs will be synchronized.

7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode

The DAC34SH84 allows exact phase alignment between multiple devices even when operating with the internal PLL clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal.

For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state by setting pll_ndivsync_ena in register config24 to 1. The SYNC signal resets the PLL N dividers with a rising edge, and the timing relationship t_{s(SYNC_PLL)} and t_{h(SYNC_PLL)} are relative to the reference clock presented on the DACCLK pin.

Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the pll_ndivsync_ena bit after resetting the PLL dividers). Besides the t_{s(SYNC_PLL)} and t_{h(SYNC_PLL)} requirement between SYNC and DACCLK, there is no additional required timing relationship between the SYNC and ISTR signals or between DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK and SYNC signals are distributed from device to device with the lowest skew possible.

Figure 86. Synchronization System in Dual Sync Sources Mode with PLL Enabled

The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the DAC34SH84 devices have a DACCLK and OSTR signal and must be carried out on each device.

1. Start up the device as described in the power-up sequence. Set the DAC34SH84 in Dual Sync Sources mode and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to 1).
2. Reset the PLL dividers with a rising edge on SYNC.
3. Disable PLL dividers resetting.
4. Sync the clock divider and FIFO pointers.
5. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
6. Disable clock divider sync by setting clkdiv_sync_ena to 0 in register config0.

After these steps all the DAC34SH84 outputs will be synchronized.

7.4.1.3 Multi-Device Operation: Single Sync Source Mode

In Single Sync Source mode, the FIFO write and read pointers are reset from the same sync source, either ISTR or SYNC. Although the FIFO in this mode can still absorb the data delay differences due to variations in the digital source output paths or board level wiring it is impossible to guarantee data will be read from the FIFO of different devices simultaneously thus preventing exact phase alignment.

In Single Sync Source mode the FIFO read pointer reset is handoff between the two clock domains (DATACLK and FIFO OUT CLOCK) by simply re-sampling the write pointer reset. Since the two clocks are asynchronous there is a small but distinct possibility of a meta-stability during the pointer handoff. This meta-stability can cause the outputs of the multiple devices to slip by up to 2 DAC clock cycles.

When the PLL is enabled with Single Sync Source mode, the FIFO read pointer is not synchronized by the OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section.

Figure 87. Multi-Device Operation in Single Sync Source Mode

7.5.1 Power-Up Sequence

The following startup sequence is recommended to power-up the DAC34SH84:

1. Set TXENA low
2. Supply all 1.35-V voltages (DACVDD, CLKVDD), 1.3-V voltages (DIGVDD, VFUSE), and 3.3-V voltages (AVDD, IOVDD, and PLLAVDD). The 1.2-V and 3.3-V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after the SIF register programming.
4. Toggle the RESETB pin for a minimum 25 ns active low pulse width.
5. Program the SIF registers.
6. Program fuse_sleep (config27, bit<11>) to put the internal fuses to sleep.
7. FIFO configuration needed for synchronization:
   1. Program syncsel_fifoin(3:0) (config32, bit<15:12>) to select the FIFO input pointer sync source.
   2. Program syncsel_fifoout(3:0) (config32, bit<11:8>) to select the FIFO output pointer sync source.
   3. Program syncsel_fifo_input(1:0) (config31, bit<3:2>) to select the FIFO input sync source.
8. Clock divider configuration needed for synchronization:
   1. Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source.
   2. Program clkdiv_sync_ena (config0, bit<2>) to 1 to enable clock divider sync.
   3. For multi-DAC synchronization in PLL mode, program pll_ndivsync_ena (config24, bit<11>) to 1 to synchronize the PLL N-divider.
9. Provide all LVDS inputs (D[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N and PARITYP/N) simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.
   1. For Single Sync Source Mode where either ISTRP/N or SYNCP/N is used to sync the FIFO, a single rising edge for FIFO and clock divider sync is recommended. Periodic sync signal is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer.
   2. For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.
   3. For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL N-divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as long as the t_{(SYNC_PLL)} setup and hold timing requirement is met with respect to the reference clock source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point.
10. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed for synchronization:
    1. For Single Sync Source Mode where the clock divider sync source is either ISTRP/N or SYNCP/N, clock divider syncing must be disabled after DAC34SH84 initialization and before the data transmission by setting clkdiv_sync_ena (config0, bit 2) to 0.
    2. For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time.
    3. Optionally, to prevent accidental syncing of the FIFO when sending the ISTRP/N or SYNCP/N pulse to other digital blocks such as NCO, QMC, etc, disable FIFO syncing by setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000 after the FIFO input and output pointers are initialized. If the FIFO and sync remain enabled after initialization, the ISTRP/N or SYNCP/N pulse must occur in ways to not disturb the FIFO operation. Refer to the INPUT FIFO section for detail.
    4. Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit<11>) to 0.
11. Enable transmit of data by asserting the TXENA pin or set sif_txenable to 1.
12. At any time, if any of the clocks (that is, DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 7 through 11. Program the FIFO configuration and clock divider configuration per steps 7 and 8 appropriately to accept the new sync pulse or pulses for the synchronization.

7.5.2 Example Start-Up Routine

Table 11. Register Map⁽¹⁾

7.6.1 Register Descriptions

Table 15. Register Name: config3 – Address: 0x03, Default: 0xF000

Register Name	Address	Bit	Name	Function	Default Value
config3	0x03	15:12	coarse_dac(3:0)	Scales the output current in 16 equal steps.	1111
		11:8	Reserved	Reserved for factory use	0000
		7:1	Reserved	Reserved for factory use	0000 000
		0	sif_txenable	When set, the internal value of TXENABLE is set to 1. To enable analog output data transmission, set sif_txenable to 1 or pull the CMOS TXENA pin (N9) to high. To disable analog output, set sif_txenable to 0 and pull the CMOS TXENA pin (N9) to low.	0