In many applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely synchronized such that their outputs are phase aligned. The DAC38RFxx achieves the deterministic latency using SYSREF (JESD204B Subclass 1).

SYSREF is generated from the same clock domain as DACCLK. After having resynchronized its local multiframe clock (LMFC) to SYSREF, the DAC will request a link re-initialization through SYNC interface. Processing of the signal on the SYSREF input can be enabled and disabled through the SPI interface.

The SYSREF capture circuit and the timing requirements relative to device clock are described in SYSREF Capture Circuit.