Two complex data streams of 20MHz LTE data generated in a baseband processor (FPGA/ASIC) is formatted based on Table 7-18 and transmitted to DAC38RF8xx. Inside DAC38RF8xx, the complex input data at a rate of 368.64 MSPS is interpolated 24 times to the final output sampling rate of 8847.36 MSPS. This enables the final RF output to be positioned in the first Nyquist zone for minimal attenuation due to sinc(x) roll off. After interpolation, the output complex data stream is digitally mixed to the final RF frequencies. The digital mixing eliminates system imperfections such as local oscillator (LO) feed-through and sideband images that are inherent in analog mixers. Detailed block diagram is shown in (Figure 8-3)

To simplify the system clocking, a low frequency clock (or device clock) is provided as a reference to the on-chip PLL (Internal PLL/VCO) of DAC38RF8xx. The PLL generates a low phase noise, high frequency sampling clock from the low frequency reference.

Figure 8-3 Dual Band LTE Downlink Transmitter Block Diagram