The DAC38RFxx has both a single ended clock input DACCLKSE and a differential clock input DACCLK+/- to clock the device. The clock input is selected by field SEL_EXTCLK_DIFFSE in register CLK_PLL_CFG (8.5.79). The DAC38RFxx can be clocked directly with a high frequency input clock at the DAC sample rate (PLL Bypass Mode), or an optional on-chip low-jitter phase-locked loop (PLL) can be used to generate the high frequency DAC sample clock internally from a lower frequency reference clock input (PLL Mode).