8.3.1 SerDes Inputs

The DAC38RFxx RX [0..7]+/- differential inputs are each internally terminated to a common point via 50 Ω, as shown in Figure 35.

Figure 35. Serial Lane Input Termination

Common mode termination is via a 50 pF capacitor to GND. The common mode voltage and termination of the differential signal can be controlled in a number of ways to suit a variety of applications via field TERM in register SRDS_CFG2 (8.5.87), as described in Table 1.

Input data is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm. The polarity of RX+ and RX- can be inverted by setting the bit of the corresponding lane in field INVPAIR in register SRDS_POL (8.5.88) to “1”. This can potentially simplify PCB layout and improve signal integrity by avoiding the need to swap over the differential signal traces.

Due to processing effects, the devices in the RX+ and RX- differential sense amplifiers will not be perfectly matched and there will be some offset in switching threshold. The DAC38RFxx contains circuitry to detect and correct for this offset. This feature can be enabled by setting ENOC in register SRDS_CFG1 (8.5.86) to “1”. It is anticipated the most users will enable this feature. During the compensation process, LOOPBACK in register SRDS_CFG1 (8.5.86) must be set to “00”.

8.3.2 SerDes Rate

The DAC38RFxx has eight configurable JESD204B serial lanes. The highest speed of each SerDes lane is 12.5 Gbps. Because the primary operating frequency of the SerDes is determined by its reference clock and PLL multiplication factor, there is a limit on the lowest SerDes rate supported. To support lower speed application, each receiver should be configured to operate at half, quarter or eighth of the full rate via field RATE in register SRDS_CFG2 (8.5.87). Refer to Table 2 for details.

8.3.3 SerDes PLL

The DAC38RFxx has two integrated PLLs, one PLL is to provide the clocking of DAC; the other PLL is to provide the clocking for the high speed SerDes. The reference frequency of the SerDes PLL can be in the range of 100-800 MHz nominal, and 300-800 MHz optimal. The reference frequency is derived from DACCLK divided down by the value in field SerDes_REFCLK_DIV in register SRDS_CLK_CFG (8.5.84), as shown in Figure 36. Field SerDes_CLK_SEL in register SRDS_CLK_CFG (8.5.84) determines if the DACCLK input or DAC PLL output is used as the source of the SerDes PLL reference. If the DACCLK input is used, a pre-divider set by field SerDes_REFCLK_PREDIV in register SRDS_CLK_CFG (8.5.84) should be used to reduce the frequency of the DACCLK.

Figure 36. Reference Clock of SerDes PLL

During normal operation, the clock generated by PLL is 4-25 times the reference frequency, according to the multiply factor selected via the field MPY] in register SRDS_PLL_CFG (8.5.85). In order to select the appropriate multiply factor and reference clock frequency, it is first necessary to determine the required PLL output clock frequency. The relationship between the PLL output clock frequency and the lane rate is determined by field RATE in register SRDS_CFG2 (8.5.87) is shown in Table 3. Having computed the PLL output frequency, the reference frequency can be obtained by dividing this by the multiply factor specified via MPY.

The wide range of multiply factors combined with the different rate modes means it is often possible to achieve a given line rate from multiple different reference frequencies. The configuration which utilizes the highest reference frequency achievable is always preferable.

The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop filter depending on the operating frequency of the VCO. If the PLL output frequency is below 2.17 GHz, VRANGE in register SRDS_PLL_CFG (8.5.84) should be set high.

Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock by setting the appropriate loop bandwidth via field LB in register SRDS_PLL_CFG (8.5.84). The loop bandwidth is obtained by dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and PLL output frequency as shown in Table 5.

An approximate loop bandwidth of 8 – 30 MHz is suitable and recommended for most systems where the reference clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input cell, but of low quality, an approximate loop bandwidth of less than 8 MHz may offer better performance. For systems where the reference clock is cleaned via an ultra-low jitter LC-based cleaner PLL, a high loop bandwidth up to 60 MHz is more appropriate. Note that the use of ultra-high loop bandwidth setting is not recommended for PLL multiply factor of less than 8.

A free running clock output is available when field ENDIVCLK in register SRDS_PLL_CFG (8.5.85) is set high. It runs at a fixed divided-by-80 of the PLL output frequency and can be output on the ALARM pin by setting field DTEST to “0001” (lanes 0 – 3) or “0010” (lanes 4 – 7) in register DTEST (8.5.76).

8.3.4 SerDes Equalizer

All channels of the DAC38RFxx incorporate an adaptive equalizer, which can compensate for channel insertion loss by attenuating the low frequency components with respect to the high frequency components of the signal, thereby reducing inter-symbol interference. Figure 37 shows the response of the equalizer, which can be expressed in terms of the amount of low frequency gain and the frequency up to which this gain is applied (i.e., the frequency of the ’zero’). Above the zero frequency, the gain increases at 6 dB/octave until it reaches the high frequency gain.

Figure 37. Equalizer Frequency Response

The equalizer can be configured via fields EQ and EQHLD in register SRDS_CFG1 (8.5.86). Table 6 and Table 7 summarize the options. When enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain should be increased or decreased. The decision logic is implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not possible to specify a generally applicable absolute limit. However, assuming random data, the maximum lock time will be 6x106 divided by the CDR activity level. For field CDR in register SRDS_CFG1 (8.5.86) = 110, the activity level is 1.5 x 10⁶ UI.

When EQ = 0, finer control of gain boost is available using the EQBOOST IEEE1500 tuning chain field, as shown in Table 8.

When EQ is set to 010 or 011, the equalizer is reconfigured to provide analytical data about the amount of pre and post cursor equalization respectively present in the received signal. This can in turn be used to adjust the equalization settings of the transmitting link partner, where a suitable mechanism for communicating this data back to the transmitter exists. Status information is provided by setting field DTEST in register DTEST (8.5.76) to “0111” for EQOVER and “0110” for EQUNDER. The procedure is as follows:

1. Enable the equalizer by setting fields EQHLD low and EQ to “001” (register SRDS_CFG1 8.5.86). Allow sufficient time for the equalizer to adapt;
2. Set EQHLD to 1 to lock the equalizer and reset the adaption algorithm. This also causes both EQOVER and EQUNDER to become low;
3. Wait at least 48 UI, and proportionately longer if the CDR activity is less than 100%, to ensure the 1 on EQHLD is sampled and acted upon;
4. Set EQ to “010” or “011”, and EQHLD to 0. The equalization characteristics of the received signal are analysed (the equalizer response will continue to be locked);
5. Wait at least 150 × 10³ UI to allow time for the analysis to occur, proportionately longer if the CDR activity is less than 100%;
6. Examine EQOVER and EQUNDER for results of analysis
   • If EQOVER is high, it indicates the signal is over equalized;
   • If EQUNDER is high, it indicates the signal is under equalized;
7. Set EQHLD to 1;
8. Repeat items 3–7 if required;
9. Set EQ to “001”, and EQHLD to 0 to exit analysis mode and return to normal adaptive equalization.

8.3.5 JESD204B Descrambler

The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x¹⁴ + x¹⁵. From the JESD204B specification, the scrambling/descrambling process only occurs on the user data, not on the code group synchronization or the ILA sequence. Each multi-DUC has a separate descrambler that can be enabled independently. The descrambler is enabled by field SCR in the multi-DUC paged register JESD_N_HD_SCR (8.5.49).

8.3.6 JESD204B Frame Assembly

The DAC38RFxx may be programmed as a single or dual DAC device, with one JESD RX block designated for each DAC. The two JESD RX blocks can be programmed to operate as two separate links or as a single link.

The JESD204B defines the following parameters:

• L is the number of lanes
• M is the number of I or Q streams per device (2 = 1 IQ pair, 4 = 2 IQ pairs, 8 = 4 IQ pairs)
• F is the number of octets per frame clock period
• S is the number of samples per frame
• HD is the High-Density bit which controls whether a sample may be divided over more lanes
• N = NPRIME is the number of bits per sample (12 or 16 - bits)

Fields K and L are found in multi-DUC paged register JESD_K_L (8.5.46), M and S in multi-DUC paged register JESD_M_S (8.5.48), and N, NPRIME and HD in multi-DUC paged register JESD_N_HD_SCR (8.5.49).

Table 9 lists the available JESD204B formats, interpolation rates and sample rate limits for the DAC38RFxx. The ranges are limited by the SerDes PLL VCO frequency range, the SerDes PLL reference clock range, the maximum SerDes line rate, and the maximum DAC sample frequency. Table 10 through Table 22 lists the frame formats for each mode. In the frame format tables, i CH (N) [x:y] and q CH (N) [x:y] are bits x through y of the I and Q samples at time N of DUC channel CH. If [x..y] is not listed, the full sample is assumed. For example, i0(0)[15:8] are bits 15 – 8 of the I sample at time 0 of DUC #0, and q1(1) is the full Q sample at time 1 of DUC #1.

Table 14. JESD204B Frame Format for LMFSHd = 44210

Table 15. JESD204B Frame Format for LMFSHd = 12410

Table 16. JESD204B Frame Format for LMFSHd = 24410

Table 17. JESD204B Frame Format for LMFSHd = 44210

Table 18. JESD204B Frame Format for LMFSHd = 88210

Table 19. JESD204B Frame Format for LMFSHd = 24410

Table 20. JESD204B Frame Format for LMFSHd = 48410

Table 21. JESD204B Frame Format for LMFSHd = 24310

Table 22. JESD204B Frame Format for LMFSHd = 48310

8.3.7 SYNC Interface

The DAC38RFxx JESD204B interface has two differential SYNC outputs called SYNC0 and SYNC1 to support one or two links. Alternatively, GPO0 and GPO1 can be used to output SYNC as a single-ended CMOS level. Each of the differential or CMOS outputs is enabled by a 2-bit register (fields GPO0_SEL, GPO1_SEL, SYNC0B_SEL, SYNC1B_SEL in register IO_CONFIG 8.5.2), with bit 0 enabling multi-DUC1 SYNC and bit 1 enabling multi-DUC2 SYNC. If both are enabled, the SYNC\ signals are OR’ed.

The SYNC signal can be asserted low by the receiver either to make a synchronization request to initialize/reinitialize the link or to report an error to the transmitter. Synchronization requests must have a minimum duration of five frames plus nine octets rounded up to the nearest whole number of frames. To report an error, the SYNC signal is asserted for exactly two frames. The transmitter interprets any negative edge of its SYNC input as an error and any SYNC assertion lasting four frames or longer as a synchronization request. See the following sections in the standard for more details.

• 7.6.3 Errors requiring re-initialization
• 7.6.4 Error reporting via SYNC interface
• 8.4 SYNC signal decoding

8.3.8 Single or Dual Link Configuration

The DAC38RFxx JESD204B interface can be configures with one or two links. The advantage of using two links, one for each DAC, is that one link can be re-established without affecting the other link and DAC.

The configuration for each mode of operation are:

1. Dual DAC, dual link
   1. Program fields OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data off of the appropriate SerDes lane.
   2. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for each multi-DUC enable the lanes used.
   3. Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) should be ‘0’ (default).
2. Dual DAC, single link
   1. Program OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data off the appropriate SerDes lane.
   2. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for each multi-DUC enable the lanes used.
   3. Set field ONE_LINK_ONLY to ‘1’ to configure TXENABLE output.
3. Single DAC, single link
   1. Set Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) to ‘1’ to gate clocks to unused multi-DUC2 for power savings.
   2. ONE_LINK_ONLY bit does not matter in this case.

8.3.9 Multi-Device Synchronization

In many applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely synchronized such that their outputs are phase aligned. The DAC38RFxx achieves the deterministic latency using SYSREF (JESD204B Subclass 1).

SYSREF is generated from the same clock domain as DACCLK. After having resynchronized its local multiframe clock (LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the signal on the SYSREF input can be enabled and disabled via the SPI interface.

The SYSREF capture circuit and the timing requirements relative to device clock are described in SYSREF Capture Circuit.

8.3.10 SYSREF Capture Circuit

The JESD204B standard for Device Subclass 1 introduces a SYSREF signal that can be used as a global timing reference to align the phase of the internal local multiframe clock (LMFC) and frame clock across multiple devices. This allows the system to achieve deterministic latency and align data samples across several data converters. The SYSREF signal accomplishes this goal by identifying a device clock edge for each chip that can be used as an alignment reference. In particular, the LMFC and frame clock align to the device clock edge upon which the SYSREF transition from “0” to “1” is sampled. SYSREF may be periodic, one-shot, or “gapped” periodic and its period must be a multiple of the LMFC period.

Figure 38. SYSREF Signal Timing

With high-speed device clocks, the phase of the SYSREF signals relative to the device clock must meet the setup/hold time requirements of each individual device clock. Historically, this has been done by controlling the board-level routing delay and/or employing commercial clock distribution capable of generating device clocks and SYSREF signals with programmable delays and with the option of splitting SYSREF into multiple SYSREFS, each with its own fine-tuned delay. Since the DAC38RFxx family supports device clock frequencies up to 9 GHz, a SYSREF capture circuit is includes in the DAC38RFxx that allows a relaxation in meeting the device clock setup and hold.

The SYSREF capture circuit provides:

• tolerance to manufacturing and environmental variations in SYSREF phase
• immunity to sampling errors due to setup/hold/meta-stability
• information about phase of SYSREF relative to DAC clock inside the data converter
• software compensation for phase misalignment due to PCB design errors

The concepts behind the SYSREF capture scheme are illustrated in Figure 39.

Figure 39. SYSREF Capture Strategy and Phase Tolerance Windows

To understand Figure 39, to begin with we’ll ignore the SYSREF phase tolerance windows in the lower portion of the figure and focus on the blue clock waveform at the top of the figure. This waveform represents the device clock input to a particular DAC chip. The green arrows, labeled “R” and “F”, correspond to the rising and falling edges of this clock (ignoring for the moment the additional arrows labeled “ER” and "EF”). Lower frequency devices captured SYSREF only on the rising edge of the device clock, the new scheme samples SYSREF on the falling edge as well, which provides more flexibility when optimizing the setup and hold time of the SYSREF capture path. Moreover, each time a rising SYSREF edge is captured, the chip remembers the clock phase during which the event occurred, and the system designer can later read back the phase information to observe the SYSREF timing relative to the device clock at the internal capture point. If SYSREF transitions close to the rising or falling clock edge sampling points the capture flop setup and hold time may not be met and the observed phase may be unreliable and subject to meta-stability phenomenon.

To reduce the sensitivity to setup/hold/meta-stability concerns an “early” version of the device clock is generated within the DAC and additional SYSREF samples are taken at the “early falling” and “early rising” edges of the clock (labeled “EF” and “ER”, respectively, in Figure 39). The resulting set of four samples is used to narrow down the timing of the rising SYSREF edge to one of four possible clock phases. If the rising SYSREF transition takes place between the “EF” and “F” samples, then SYSREF is said to occur in phase θ1. Similarly, if it takes place between the “F” and “ER” samples, then it is said to occur in phase θ2. If SYSREF transitions between the “ER” and “R” samples, then it is said to occur in phase θ3. And, finally, if the SYSREF rising edge event happens between the “R” and “EF” samples, then it is said to occur in phase θ4. As mentioned before, the chip remembers all observed SYSREF phases and the user can later read them back. Since the delay between “early” and “on time” versions of the clock is intentionally chosen to be larger than the setup/hold/meta-stability window, at most one of the four samples can be affected even when the SYSREF transitions right at one of the four sampling points. Thus, the uncertainty in the observed SYSREF timing is limited to adjacent phases, and with twice as many sampling phases the resolution of the timing information is improved by a factor of two.

Referring to the lower portion of Figure 39, the user can now see how this information regarding the observed SYSREF phases is used to devise a reliable SYSREF capture methodology with a high degree of tolerance to manufacturing and environmental variations in SYSREF phase. Based on the SYSREF phases observed for a particular DAC chip during system characterization, the system designer can select one of four so-called “phase tolerance window” options (denoted “’00”, “01”, “10”, and “11”) to maximize immunity to manufacturing and environmental variations. For example, consider the default phase tolerance window labeled “window=00” in the figure. If, during characterization, the system designer observes (by reading back the recorded phase observations) that the rising SYSREF edge nominally occurs in either θ1 or θ2 or both (i.e. θ12) then he would program that particular DAC chip to use phase tolerance window “00”. This mapping is indicated in the figure with the label “θ1|θ12|θ2: window=00”. Having programmed the device to use window “00”, all future SYSREF events that occur in θ1 or θ2 would trigger the LMFC and frame clock to be aligned using the following rising clock edge as the alignment reference (as indicated by the red arrow pointing to rising clock edge “R” and labeled “Window=00/01 alignment edge”).

The full extent of each phase tolerance window is indicated in the figure using “box and whisker” plots. For the “window=00” example, the “box” portion of the plot indicates that the phase tolerance window is centered on θ12 (to be precise on the boundary between θ1 and θ2) and the “whisker” portion indicates that even if the rising edge of SYSREF occurs as early as the preceding θ4 or as late as the following θ3 it still results in LMFC and frame clock alignment to the same rising clock edge indicated by the red arrow labeled “Window=00/01 alignment edge”. When programmed for phase tolerance window “00”, the DAC chip is tolerant to variations in the SYSREF timing ranging from a rising SYSREF edge that occurs just after one rising edge of clock to just before the next rising edge of the clock. The qualifying phrases “just after” and “just before” are used here to indicate that the SYSREF transition must occur far enough away from the rising edges of the clock to avoid setup/hold violations and prevent the device from concluding that the SYSREF transition has crossed out off the phase tolerance window when in fact it has not. The tolerance range for window “00” is from rising clock edge to rising clock edge and is indicated in the figure by the green text labeled “tolerance = R↔R”.

Following the above example, if characterization reveals SYSREF timing centered on θ23 then phase tolerance window “01” (with tolerance for SYSREF rising edge events from EF to EF) should be chosen. Notice that this option is tolerant even to rising SYSREF edges that occur after the rising device clock edge (i.e. in θ4) and will treat them just as if they had occurred in one of the earlier three phases, aligning to the same rising device clock edge indicated by the red arrow labeled “Window=00/01 Alignment Edge”. This allows the system designer to tolerate PCB design errors and/or environmental and manufacturing variations – achieving his intended alignment without having to make physical changes to the board to adjust the SYSREF timing.

Similarly, if characterization indicates that SYSREF timing is centered on θ34 or θ41 then phase tolerance window “10” or “11” can be selected, resulting in tolerance for “F↔F” or “ER↔ER” SYSREF timing, respectively. Note, however, that in these two cases the alignment reference edge is by default taken to be the subsequent rising edge of the device clock. Since this may not be the desired behavior, the DAC38RFxx allows the user to program in an optional alignment offset of θ1 if the default offset of 0 does not achieve the desired alignment. This feature is illustrated in Figure 40 where the user can see that by setting the alignment offset to -1, phase tolerance windows “10” and “11” can be made to trigger alignment to the earlier rising device clock edge used by windows “00” and “01”. Alternatively, the window “00” and “01” alignment edge can be pushed one cycle later by setting their alignment offset to +1.

Figure 40. Optional SYSREF Alignment Offset

Several important controls related to SYSREF alignment and capture timing are contained in register SYSR_CAPTURE (8.5.78). For example, as mentioned before, the device is capable of monitoring the observed phases of the rising SYSREF edge events; however, in order to avoid unwanted noise coupling from the SYSREF circuits into the DAC output, the SYSREF monitoring circuits are disabled by default. Field SYSR_STATUS_ENA enables SYSREF status monitoring. Field SYSR_PHASE_WDW contains the the phase tolerance window selected for normal operation, which is optimized during characterization. Field SYSR_ALIGN_DLY contains the control that allows the system designer to optionally offset the SYSREF alignment event by ±1 device clock cycles. Field SYSR_STATUS_ENA enables the SYSREF capture alignment accumulation and will generate alarms when enabled. Writing a “1” to field SYSR_ALIGN_SYNC clears the accumulated SYSREF alignment statistics. The SYSREF alignment block can be bypassed completely by field SYSREF_BYPASS_ALIGN, in which case SYSREF is latched by the rising edge of DACCLK.

When field SYSR_STATUS_ENA is high the device records the phase associated with each SYSREF event for use in characterizing the SYSREF capture timing and selecting an appropriate phase tolerance window. The phase data is available in two forms. First, each of the four phases has a corresponding “sticky” alarm flag indicating which phases have been observed since the last time the register was cleared. In addition, the device also accumulates statistics on the relative number of occurrences of each phase spanning multiple SYSREF events using saturating 8-bit counters. These accumulated real-time SYSREF statistics allow us to account for time-varying effects during characterization such as potential timing differences between the 1st and Nth edges in a “gapped” SYSREF pulse train. The counters are fields PHASE1_CNT and PHASE2_CNT in register SYSREF12_CNT (8.5.10), PHASE3_CNT and PHASE4_CNT in register SYSREF34_CNT (8.5.11), and ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT in register SYSREF_ALIGN_R (8.5.9).

The accumulated SYSREF statistics can be cleared by writing ‘1’ to SYSR_ALIGN_SYNC. This sync signal affects only the SYSREF statistics monitors and does not cause a sync of any other portions of the design. Before collecting phase statistics, the user must first enable the SYSREF status monitoring logic by setting the SYSR_STATUS_ENA bit. The user must then generate a repeating SYSREF input before using SYSR_ALIGN_SYNC to clear the statistic counters. This is necessary to flush invalid data out of the status pipeline.

The “sticky” alarm flags indicating which of the four phases have been observed since the last SYSR_ALIGN_SYNC write of ‘1’ are fields ALM_SYSRPHASE1 to ALM_SYSRPHASE4 and are contained in the ALM_SYSREF_DET register (8.5.6).

8.3.11 JESD204B Subclass 0 support

Some functionality has been implemented to support Subclass 0 operation. Note that programming the SUBCLASSV configuration parameter has no functional impact on the logic. The value programmed for SUBCLASSV is only used in the initial lane alignment (ILA) sequence. The following configuration parameters are used to support Subclass 0 operation:

• Field SYSREF_MODE in register JESD_SYSR_MODE (8.5.56) = 0
• Field DISABLE_ERR_RPT in register JESD_ERR_OUT (8.5.53) = 1
• Field MIN_LATENCY_ENA in register JESD_MATCH (8.5.50) = 1

8.3.12 SerDes Test Modes through Serial Programming

The DAC38RFxx supports a number of basic pattern generation and verification of SerDes via the serial interface. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating 0/1 pattern and a 20-bit user-defined sequence. The 2⁷ - 1, 2³¹ - 1 or 2²³ – 1 sequences implemented can often be found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation and verification selection is via field TESTPATT in register SRDS_CFG1 (8.5.86), as shown in Table 23.

Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM terminal by setting field DTEST in register DTEST (8.5.76) to “0011”.

8.3.13 SerDes Test Modes through IEEE 1500 Programming

DAC38RFxx also provide a number of advanced diagnostic capabilities controlled by the IEEE 1500 interface. These are:

• Accumulation of pattern verification errors;
• The ability to map out the width and height of the receive eye, known as Eye Scan;
• Rreal-time monitoring of internal voltages and currents;

The SerDes blocks support the following IEEE1500 instructions:

The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver or transmitter) and tail. DAC38RFxx uses two SerDes receiver blocks R0 and R1, each of which contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head, receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for each instruction is given as follows:

8.3.14 Error Counter

All receive channels include a 12-bit counter for accumulating pattern verification errors. This counter is accessible via the ECOUNT IEEE1500 Char field. It is an essential part of the eye scan capability (see the Eye Scan section).

The counter increments once for every cycle that the TESTFAIL bit is detected. The counter does not increment when at its maximum value (i.e., all 1s). When an IEEE1500 capture is performed, the count value is loaded into the ECOUNT scan elements (so that it can be scanned out), and the counter is then reset, provided NCOR is set high.

ECOUNT can be used to get a measure of the bit error rate. However, as the error rate increases, it becomes less accurate due to limitations of the pattern verification capabilities. Specifically, the pattern verifier checks multiple bits in parallel (as determined by the Rx bus width), and it is not possible to distinguish between 1 or more errors.

8.3.15 Eye Scan

All receive channels provide features which facilitate mapping the received data eye or extracting a symbol response. A number of fields accessible via the IEEE1500 Char scan chain allow the required low level data to be gathered. The process of transforming this data into a map of the eye or a symbol response must then be performed externally, typically in software.

The basic principle used is as follows:

• Enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the normal data sample;
• Apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity;
• Apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken;
• Reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset adjustments;
• Run in this state for a period of time, periodically checking to see if any errors have occurred;
• Change voltage and/or phase offset, and repeat.

Alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a specified time interval.

Eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. The IEEE1500 Char fields used to directly control eye scan and symbol response extraction are ES, ESWORD, ES BIT SELECT, ESLEN, ESPO, ESVO, ESVO OVR, ESRUN and ESDONE. Eye scan errors are accumulated in ECOUNT.

The required eyescan mode is selected via the ES field, as shown in Table 29. When enabled, only data from the bit position within the 20-bit word specified via ES BIT SELECT is analyzed. In other words, only eye scan errors associated with data output at this bit position will accumulate in ECOUNT. The maximum legal ES BIT SELECT is 10011.

When ES[3] = 0, the selected analysis runs continuously. However, when ES[3] = 1, only the number of qualified samples specified by ESLed, as shown in Table 30. In this case, analysis is started by writing a 1 to ESRUN (it is not necessary to set it back to 0). When analysis completes, ESDONE is set to 1.

When ESVO OVR = 1, the ESVO field determines the amount of offset voltage that is applied to the eye scan data samplers associated with rxpi and rxni. The amount of offset is variable between 0 and 300 mV in increments of ~10 mV, as shown Table 31. When ES[3] = 1, ESVO OVR must be 0 to allow the optimized voltage offset to be read back via ESVO.

The phase position of the samplers associated with rxpi and rxni, is controlled to a precision of 1/32UI. When ES is not 00, the phase position can be adjusted forwards or backwards by more than one UI using the ESPO field, as shown in Table 32. In normal use, the range should be limited to ±0.5 UI (+15 to –16 phase steps).

8.3.16 JESD204B Pattern Test

The DAC38RFxx supports the following test patterns for JESD204B:

• Link layer test pattern by setting field JESD_TEST_SEQ in register JESD_LN_EN (8.5.45) and monitoring the lane alarms (1 = fail, 0 = pass)
  • Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)
  • Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)
  • Verify repeating initial lane alignment (ILA) sequence
• RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an amount of time to get an estimate of BER.
• Transport layer test pattern: implements a short transport layer pattern check based on F = 1, 2, 4 or 8. The short test pattern has a duration of one frame period and is repeated continuously for the duration of the test. Each sample has a unique value that can be identified with the position of the sample in the user data format. The sample values are such that correct sample values will never be decoded at the receiver if there is a mismatch between the mapping formats being used at the transmitter and receiver devices. This can generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted. Refer to the JESD204B standard section 5.1.6 for more details.

The DAC38RFxx expects the test samples, in a frame, transmitted by an logic device as per Table 33:

The short test pattern has duration of one frame period and is repeated continuously for the duration of the test. Each sample has a unique value that can be identified with the position of the sample in the user data format. The sample values are such that correct sample values will never be decoded at the receiver if there is a mismatch between the mapping formats being used at the transmitter and receiver devices. This can generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted.

Following are the steps required to execute the short test functionality in DAC38RFxx.

1. Configure other registers, make sure clocks are up and running.
2. Start driving short test patterns
3. Clear short test alarm by writing ‘0’ to field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67). This is a paged register, one for each Multi-DUC.
4. Enable short test by writing a ‘1’ to field SHORTTEST_ENA in register MULTIDUC_CFG2 (8.5.14).
5. Read the short test alarm from field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67). This is a paged register, one for each Multi-DUC

If the alarm read from the register is high, the short test has detected an error.

8.3.17 Multiband DUC (multi-DUC)

Each DAC output in the DAC38RFxx is supported by a dual band digital upconverter (DUC), which is called a multi-DUC.Figure 41 shows the signal processing features of each of the two multi-DUCs. The two paths are identical and independent. The SPI interface registers for the multi-DUCs are addressed through paging, with page 0 supporting multi-DUC1 and page 1 supporting multi-DUC2. Register PAGE_SET (8.5.8) is used to set the pages. Both pages can be selected at the same time to program both multi-DUCs simultaneously with the same settings.

Each multi-DUC has 2 DUC channels, called path AB and path CD. The output of one multi-DUC can be added to the signal of the other multi-DUC to allow a configuration with 4 total DUCs summed together for 1 DAC. After quadrature modulation is a sin(x)/x compensation filter, followed by the multiband summation block. The multi-band summation block had the ability to add the signals from the other multi-DUC for a combined 4 DUCs, each with independent frequency control. The final block is an output delay block with 0 – 15 sample range.

Figure 41. DAC38RFxx multi-DUC Signal Processing Block Diagram

8.3.17.2 Interpolation Filters

The digital upconverter first increases the sample rate of the IQ signal from the input sample rate to the final DAC sample rate through a series of interpolation filters. Different sets of filters are used to achieve different rates, as shown in Table 34. The interpolation rate is selected by field INTERP in register MULTIDUC_CFG1 (8.5.13).

Table 34. FIR filters Used for Different Interpolation Rates

FILTERS USED
Interpolation Rate	FIR0 (2x)	FIR1 (2x)	LPFIR0_5X	FIR2 (2x)	LPFIR0_3X	FIR3 (2x)	LPFIR1_3X
6	x				x
8	x	x		x
10	x		x
12	x	x					x
16	x	x		x		x
18	x				x		x
20	x	x	x
24	x	x		x			x

The FIR filter coefficients are shown in Table 35 The FIR filters are design with a passband BW of 0.4 x f_INPUT, a stopband attenuation of 90 dBc and ripple of < 0.001 dB. The composite frequency response for each interpolation factor are shown in Figure 42 to Figure 49.

A.

Figure 42. Composite Magnitude Response for 6x Interpolation

A.

Figure 44. Composite Magnitude Response for 10x Interpolation

A.

Figure 43. Composite Magnitude Response for 8x Interpolation

A.

Figure 45. Composite Magnitude Response for 12x Interpolation

A.

Figure 46. Composite Magnitude Response for 16x Interpolation

A.

Figure 48. Composite Magnitude Response for 20x Interpolation

A.

Figure 47. Composite Magnitude Response for 18x Interpolation

A.

Figure 49. Composite Magnitude Response for 24x Interpolation

Table 35. FIR Filter Coefficients

tap	FIR0	FIR1	LPFIR0_5X	FIR2	LPFIR0_3X	FIR3	LPFIR1_3X	INVSINC
1	6	-12	-6	29	-14	3	25	1
2	0	0	-22	0	-61	0	88	-4
3	-19	84	-51	-214	-125	-25	22	13
4	0	0	-89	0	-95	0	-576	-50
5	47	-336	-117	1209	181	150	-1764	592
6	0	0	-106	2048	681	256	-2263	-50
7	-100	1006	-18	1209	972	150	491	13
8	0	0	171	0	347	0	8139	-4
9	192	-2691	449	-214	-1475	-25	18625	1
10	0	0	745	0	-3519	0	26365
11	-342	10141	930	29	-3528	3	26365
12	0	16384	841		707		18625
13	572	10141	338		9337		8139
14	0	0	-618		19445		491
15	-914	-2691	-1892		26299		-2263
16	0	0	-3147		26299		-1764
17	1409	1006	-3872		19445		-576
18	0	0	-3500		9337		22
19	-2119	-336	-1564		707		88
20	0	0	2121		-3528		25
21	3152	84	7336		-3519
22	0	0	13430		-1475
23	-4729	-12	19426		347
24	0		24231		972
25	7420		26904		681
26	0		26904		181
27	-13334		24231		-95
28	0		19426		-125
29	41527		13430		-61
30	65536		7336		-14
31	41527		2121
32	0		-1564
33	-13334		-3500
34	0		-3872
35	7420		-3147
36	0		-1892
37	-4729		-618
38	0		338
39	3152		841
40	0		930
41	-2119		745
42	0		449
43	1409		171
44	0		-18
45	-914		-106
46	0		-117
47	572		-89
48	0		-51
49	-342		-22
50	0		-6
51	192
52	0
53	-100
54	0
55	47
56	0
57	-19
58	0
59	6

8.3.17.4 Digital Quadrature Modulator

Each DUC in the DAC38RFxx has digital quadrature modulator (DQM) blocks with independent Numerically Controlled Oscillators (NCO) that converts the complex input signal to a real signal with flexible frequency placement between 0 and f_DAC/2. The NCOs are enabled by fields NCOAB_ENA and NCOCD_ENA in register MULTIDUC_CFG2 (8.5.14). The NCOs have 48-bit frequency registers (FREQ_NCOAB (8.5.25) and FREQ_NCOCD (8.5.26)) and 16-bit phase registers (PHASE_NCOAB (8.5.23) and PHASE_NCOCD (8.5.24)) that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 50.

Figure 50. NCO Block Diagram

Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is selected by fields SYNCSEL_NCOAB and SYNCSEL_NCOCD in register SYNCSEL1 (8.5.29). The frequency word in the FREQ_NCOAB and FREQ_NCOCD registers are added to the accumulators every clock cycle, f_DAC.

The frequency and phase offset of the NCOs are:

Equation 1.

Equation 2.

Treating the complex channels as complex vectors of the form I + j Q, the output of the DQM is:

Equation 3.

Equation 4.

Where t is the time since the last resetting of the NCO accumulator and the fields MIXERAB_GAIN and MIXERCD_GAIN in register MULTIDUC_CFG2 (8.5.13) are either 0 or 1.

The maximum output amplitude of the DQM occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and the sine and cosine arguments are equal to an integer multiple of π/4.

With MIXERAB_GAIN or MIXERCD_GAIN = 0, the gain through the DQM is sqrt(2)/2 or -3 dB. This loss in signal power is in most cases undesirable, and it is recommended that the gain function be used to increase the signal by 3 dB to compensate. With MIXERAB_GAIN or MIXERCD_GAIN = 1, the gain through the DQM is sqrt(2) or +3 dB, which can cause clipping of the signal if I_IN(t) and Q_IN(t) are simultaneously near full scale amplitude and should therefore be used with caution.

8.3.17.5 Low Power Coarse Resolution Mixing Modes

In addition to the NCO the DAC38RFxx also has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing frequencies ±N x f_DAC/8. Using the coarse mixer instead of the full mixers will result in lower power consumption.

Treating the two complex channels as complex vectors of the form I(t) + j Q(t), the outputs of the coarse mixer is equivalent to:

Equation 5.

Equation 6.

Where f_{CMIX_AB} and f_{CMIX_CD} and the fixed mixing frequency selected by fields CMIX_AB or CMIX_CD in register CMIX (8.5.21). The coarse mixer blocks are disabled by setting CMIX_AB and CMIX_CD to 0x0.

The NCO and coarse mixers can be enabled simultaneously, although this is not useful in most cases as the full frequency range can be covered by the NCO.

8.3.17.6 Inverse Sinc Filter

The DAC38RFxx have a 9-tap inverse Sinc filter (INVSINC) that runs at the DAC update rate (fDAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well known sin(x)/x or Sinc(x) frequency response (Figure 51, red line). The inverse sinc filter response (Figure 51, blue line) has the opposite frequency response from 0 to 0.4 x f_DAC, resulting in the combined response (Figure 51, green line). Between 0 to 0.4 x f_DAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03 dB error.

The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to INVSINC must be reduced from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, andis set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 dB). For example, if the signal input to INVSINC is at 0.25 x f_DAC, the response of INVSINC is 0.9 dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The advantage of INVSINC having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based on its frequency.

The inverse Sinc filters are enabled by field ISFIR_ENA in register MULTIDUC_CFG1 (9.5.9).

Figure 51. Composite Magnitude Spectrum for INVSINC

8.3.18 PA Protection Block

The DAC38RFxx incorporates an optional power amplifier protection (PAP) block to monitor when the input signal is two large, for example when an interface error occurs, and reduces the output signal power of the DAC. The PAP block achieves the functionality of reducing the input signal that crosses the threshold through three main sub-blocks. These are PAP trigger generation block, PAP gain state machine and GAIN block.

The PAP block keeps track of the input signal power by maintaining a sliding window accumulation of last N samples. N is selectable to be 32, 64 or 128 based on the setting (Table 38) of fields PAPAB_SEL_DLY in register PAP_CFG_AB (8.5.35) and PAPCD_SEL_DLY in register PAP_CFG_CD (8.5.36). The average amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line (N). The result is then compared against the threshold in fields PAPAB_THRESH in register PAP_CFG_AB (8.5.35) and PAPCD_THRESH in register PAP_CFG_CD (8.5.36). If the threshold is violated, gain state machine is triggered which generated gain value to ramp down the DAC output signal amplitude. After the input signal returns to normal value, the state machine ramps up the DAC output signal amplitude.

The generation of the PAP trigger as explained as follows:

• The I and Q samples are treated separately – either can trigger attenuation
• In dual DUC modes, each IQ pair is treated separately and has a separate gain block
• 8 samples at the input are put through an absolute value circuit (all 2’s complement)
• Next these values are vector summed to get a 12 bit result
• Then 12 bit result is placed into the delay line and summed into the accumulator
• The accumulator is also subtracting out the delayed 12 bit word corresponding to N = 32, N = 64 or N = 128
• Finally the accumulator output is divided down by N and rounded to 13 bits. These 13 bits are compared to the threshold in the SPI registers. A pap_trig occurs if the threshold is exceeded.

The PAP gain state machine generates the pap gain value to be applied on the output stream to reduce the output signal amplitude. The state machine below is used to control the attenuation of the DAC output and the gaining up of the signal again once the trigger is released.

Figure 52. PAP Gain State Machine

The normal operating condition for the PAP block is the NORMAL state in Figure 52. However, when the PAP block detects an error condition it sets the pap_trig signal to ‘1’ causing a state transition from NORMAL operation to the ATTENUATE state.

In the ATTENUTATE state the data path gain is scaled from 1.0 down to 0.0 by a programmable step amount set by fields PAPAB_GAIN_STEP in register PAP_GAIN_AB (8.5.31) and PAPCD_GAIN_STEP in register PAP_GAIN_CD (8.5.33). This value is always positive with the decimal place located between the MSB and MSB-1. Unity is equal to “1000000000”. Each clock cycle (16 samples) the PAP_GAIN is stepped down by PAPAB_GAIN_STEP and PAPCD_GAIN_STEP until the gain is 0.

After PAP_GAIN is 0, the state machine moves on to the WAIT state. Here a programmable counter counts clock cycles to allow the condition for the pap_trig to be fixed. Fields PAPAB_WAIT in register PAP_WAIT_AB (8.5.32) and PAPCD_WAIT in register PAP_WAIT_CD (8.5.34) are used to select the number of clock cycles (samples = 16 x PAPAB_WAIT or 16 x PAPCD_WAIT) to wait before moving to the next state. Once the WAIT counter equals zero and pap_trig=’0’, the state machine moves on to the GAIN state. If the WAIT equals 0 but pap_trig still equals ‘1’ then the state machine stays in the WAIT state until pap_trig =’0’.

8.3.19 Gain Block

The GAIN block also has additional output gain control through fields GAINAB in register GAINAB (8.5.39) and GAINCD in register GAINCD (8.5.40). Similar to PAP_GAIN value, the output gain is always positive with unity when GAINAB or GAINCD = ”010000000000”.

To reduce the power, the gain block clock has been gated whenever the pap is disabled and GAINAB or GAINCD is set to unity.

8.3.20 Output Summation

The OUTSUM block allows addition of samples from each DUC in the multi-DUC. It is also possible to add the output samples from the adjacent multi-DUC. Field OUTSUM_SEL in register OUTSUM (8.5.22) controls the summation for each multi-DUC. The functionality of the block can be represented by the following equation:

Equation 7.

In order to avoid overflow, rounding operation is performed after the addition to reduce the word size back to 16-bits. Exact number of bits rounded depends on the number of channels added. Table 39 shows the description of round after the summation.

8.3.21 Output Delay

The signal following output summation can be programmably delayed by 0-15 DACCLK cycles through field OUTPUT_DELAY in register OUTSUM (8.5.20). The block takes 16 sample words (vec16) from both the A and B paths and shifts the them to 32 sample long delay line.

8.3.22 Polarity Inversion

The signal following the output delay can be inverted by a 2’s complement conversion allowing the + and - DAC outputs to be swapped by asserting field DAC_COMPLEMENT in register MULTIDUC_CFG1 (8.5.13).

8.3.23 Temperature Sensor

The DAC38RFxx incorporates a temperature sensor block which monitors the die temperature by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDEN and SCLK. If the temperature sensor is enabled by writing a 0 to field TSENSE_SLEEP in register SLEEP_CONFIG (8.5.70), a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in field TEMPDATA in register TEMP_PLLVOLT (8.5.7). The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from register TEMP_PLLVOLT must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

8.3.24 Alarm Monitoring

The DAC38RFxx includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. All the alarm events can be accessed either through the SIP registers and/or through the ALARM output. Once an alarm is set, the corresponding alarm bit must be reset through the serial interface to allow further testing. The set of alarms includes the following conditions:

• JESD alarms
  • Fields ALM_LANEx_ERR in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):
    • multiframe alignment_error. Occurs when multiframe alignment fails
    • frame alignment error. Occurs when multiframe alignment fails
    • link configuration error. Occurs when there is wrong link configuration
    • elastic buffer overflow. Occurs when bad RBD value is used
    • elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed data
    • code synchronization error
    • 8b/10b not-in-table decode error
    • 8b/10b disparity error
  • Field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67): Occurs when the short pattern test fails.
• SerDes alarms
  • Field ALM_SD_LOTDET in register ALM_SD_DET 8.5.5): Occurs when there are loss of signal detect from SerDes lanes.
  • Fields ALM_FIFOx_FLAGS in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):
    • FIFO write error. Occurs if write request and FIFO is full.
    • FIFO write full: Occurs if FIFO is full.
    • FIFO read error. Occurs if read request and FIFO is empty.
    • FIFO read empty: Occurs if FIFO is empty.
  • Field ALM_SD0_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 0 goes out of lock.
  • Field ALM_SD1_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 1 goes out of lock.
• SYSREF alarm
  • Field ALM_SYSREF_ERR in register ALM_SYSREF_PAP (8.5.67): Occurs when the SYSREF is received at an unexpected time. If too many of these occur it will cause the JESD to go into synchronization mode again.
• DAC PLL alarm
  • Field PLL_LOCK in register ALM_SYSREF_DET (8.5.6). This register field is asserted when the PLL is unlocked. When used as an alarm output, a high signal indicates that the PLL is unlocked if the ALM_OUT_POL bit in register RESET_CONFIG is set to 1.
• PAP alarm
  • Field ALM_PAP in register ALM_SYSREF_PAP (8.5.67): Occurs when the average power is above the threshold. While any alarm_pap is asserted the attenuation for the appropriate data path is applied.

8.3.25 Differential Clock Inputs

Figure 53 shows the preferred configuration for driving the DACCLK+/- and SYSREF+/- with a differential ECL/PECL source.

Figure 53. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source

8.3.26 CMOS Digital Inputs

Figure 54 shows a schematic of the equivalent CMOS digital inputs of the DAC38RFxx. SDIO, SCLK, TCLK, SLEEP, TESTMODE and TXENABLE have internal pull-down resistors while SDEN, RESET, TMS, TDI and TRST have internal pull-up resistors. See the Specifications table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 10 kΩ.

Figure 54. CMOS Digital Equivalent Input

8.3.27 DAC Fullscale Output Current

The DAC38RFxx uses a bandgap reference and control amplifier for biasing the full-scale output current. The DAC full scale output current is set by a combination of the fixed current through the external resistor RBIAS (connected to pin BIASJ) and current from course trim current sources:

Equation 8.

The bias current IBIAS through resistor R_BIAS is defined by the on-chip bandgap reference voltage V_BG (nominally 0.9 V) and control amplifier. For normal operation, it is recommended that R_BIAS is set to 3.6 kΩ for a fixed current through R_BIAS of 250 µA. This current is scaled 128x internally, giving:

Equation 9.

The course trim current sources are configured through SPI register field DACFS in register DACFS (8.5.72),as follows:

Equation 10.

From the discussion above, the DAC full scale output current can be configured from 40 mA (DACFS[3:0] = 1111) down to 10 mA (DACFS[3:0] = 0000). In addition to the full scale signal current set by SPI register DACFS (8.5.72), an extra DC bias current is required to set the operating point of the output current sources(Table 40).

An external decoupling capacitor C_EXT of 0.1 μF should be connected externally to terminal EXTIO for compensation. R_BIAS of 3.6 kΩ is recommended for setting the full-scale output current.

8.3.28 Current Steering DAC Architecture

The DACs in the DAC38RFxx consist of a segmented array of NMOS current sources, capable of sinking a full-scale output current up to 40 mA (see Figure 55). Differential current switches direct the current to either one of the complimentary output nodes VOUT1/2+ or VOUT1/2-. These complementary output nodes are internal to the device because of the integrated balun.Complimentary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of four.

Figure 55. Current Steering DAC Architecture

Referring to Figure 55, the total output current IOUTFS is fixed, and is switched to either the + or – output by switches S(N):

Equation 11.

Since the output stage is a current sinking architecture, we will denote current into the DAC as + current, and the current flows IOUT+ and IOUT- into terminals VOUT1/2+ and VOUT1/2- respectively. IOUT+ and IOUT- can be expressed as:

Equation 12.

Equation 13.

where CODE is the decimal representation of the 14-bit DAC core data input word. Note the signal path up to the DAC is 16-bits and the 2 LSBs are truncated for the DAC core data input word.

8.3.29 DAC Transfer Function

The DAC38RFxx has a wide bandwidth integrated balun (nominally 700 MHz to 3.8 GHz passband) to convert the DAC core differential signal to a single ended signal. The single ended output is expected to drive a 50-Ω load (see Figure 56). With full-scale current of 40 mA, the theoretical output power delivered to a 50-Ω load is 4 dBm. However the actual power delivered will be less than the theoretical value and Figure 13 shows the output power across frequency.

Figure 56. Driving a 50-Ω Load

8.4.1 Clocking Modes

The DAC38RFxx has both a single ended clock input DACCLKSE and a differential clock input DACCLK+/- to clock the device. The clock input is selected by field SEL_EXTCLK_DIFFSE in register CLK_PLL_CFG (8.5.79). The DAC38RFxx can be clocked directly with a high frequency input clock at the DAC sample rate (PLL Bypass Mode), or an optional on-chip low-jitter phase-locked loop (PLL) can be used to generate the high frequency DAC sample clock internally from a lower frequency reference clock input (PLL Mode).

8.4.2 PLL Bypass Mode Programming

In PLL bypass mode a high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock the DAC38RFxx DAC cores. This mode gives the device best performance and is recommended for extremely demanding applications.

The bypass mode is selected by setting the following:

1. Set field PLL_ENA in register CLK_PLL_CFG (8.5.79) to “0” to bypass the PLL circuitry.
2. Set field PLL_SLEEP in register SLEEP_CONFIG (8.5.70) to “1” to put the PLL and VCO into sleep mode.

8.4.3 Internal PLL/VCO

The DAC38RFxx has an internal clock generation circuit consisting of a PLL and two identical VCOs connected in parallel, as shown in Figure 57.

Figure 57. Internal PLL/VCO Block Diagram

The two parallel VCOs are tuned to a target center frequency of 5.9 GHz (low VCO) in DAC38RF87 and DAC38RF97. They are tuned to a target center frequency of 8.85 GHz (high VCO) in DAC38RF86 and DAC38RF96. The field PLL_VCOSEL in register PLL_CONFIG2 (8.5.81)must always be set to 0 in DAC38RF87/97 and always set to '1' in DAC38RF86/96/88/81. Also GSMPLL_ENA in register PLL_CONFIG2 must always be set to '1' in all devices to ensure the two identical VCOs are connected in parallel. The 7 bit VCO tuning code in field PLL_VCO in register PLL_CONFIG2 is used to tune the VCO frequency in the range of 5.24 GHz to 6.72 GHz for the low VCO and 7.96 GHz to 9.0 GHz for the high VCO. For the low VCO the center VCO frequency is achieved with PLL_VCO = 63_decimal and for the high VCO the target VCO center frequency is also achieved with PLL_VCO = 63_decimal.

The supply current, and therefore; the analog signal amplitude in the VCO is controlled using the field PLL_VCO_RDAC in register PLL_CONFIG1 (8.5.80). This control signal should be set 15_decimal initially for 18 mA supply current in the VCO and ~1.4 V_PP single ended oscillation amplitude.

The PLL has no prescaler, so the DAC sample rate is the VCO frequency. In the PLL feedback path a fixed ÷ 4 frequency divider block receives the VCO output clock and divides its frequency by 4. The maximum operating frequency of the phase-frequency detector (PFD) is approximately 550 MHz. The M (feedback) clock divider takes the output clock signal from the fixed ÷4 block and divides it by a programmable ratio set by the 8-bit field in field PLL_M_M1 in register PLL_CONFIG1 (8.5.80). The programmable division ratio range is ÷1 to ÷256, and is the value of the 8 bit unsigned binary code + 1. Although it is possible to program the M divider to ÷1, ÷2 and ÷3, these values should not be used. As stated previously the PFD and CP have a finite maximum operating frequency, which is the VCO frequency divided by the fixed divider ratio multiplied by the minimum allowable M divider ratio.

Equation 14.

The N (reference) divider determines the ratio between the input reference clock frequency and the PFD operating frequency, and is set by the 5-bit field PLL_N_M1 in register CLK_PLL_CFG (8.5.79). The division ratio range is ÷1 to ÷32, and is the value of the 5-bit unsigned binary code + 1.

The charge pump output current amplitude is set using the 4-bit field PLL_CP_ADJ in in register PLL_CONFIG2 (8.5.81). The current amplitude is simply the digital code multiplied by the unit current amplitude of 100 µA. In a nominal condition, with the LF VCO running at 5.898 GHz, and with the M divider set to ÷4, the PFD will run at 368.625 MHz, and the change pump current should set to 6_decimal, which gives 600 µA charge pump output current for a good phase margin of 69 degrees. If a higher M ratio (for lower PFD frequencies) are required the charge pump output current must be increased to maintain good loop stability and prevent excessive peaking in the phase noise response. The charge pump output current setting PLL_CP_ADJ should be adjusted in relation to the feedback (M) divider ratio PLL_M_M1 according to the following table to maintain a constant phase margin of 69 degrees.

Similarly for the HF VCO running at 8.847 GHz, and with the M divider set to ÷4, the PFD will run at 552.9375 MHz as shown above. Here the change pump current should set to 6_decimal, which gives 600 µA charge pump output current for a good phase margin of 69 degrees.

8.4.4 CLKOUT

The DAC38RFxx has a programmable output clock on CLKTX+/- balls that is a divided version of the internal DAC sample clock, either with or without PLL. Two frequency dividers, either DACCLK/3 or DACCLK/4, are available by programming field CLK_TX_DIV4 in register CLK_OUT (8.5.71). The output swing voltage is programmable from approximately 125 to 1460 mV_PP-DIFF through field CLK_TX_SWING in register CLK_OUT (8.5.71).

Field CLK_TX_IDLE in register CLK_OUT (8.5.71) enables an idle state, in which the pins are driven to the proper common-mode levels in order to charge the external AC coupling caps but the clock output is disabled. The output clock circuit can be put to sleep by field CLK_TX_SLEEP in register SLEEP_CONFIG (8.5.70).

8.4.5 Serial Peripheral Interface (SPI)

The serial port of the DAC38RFxx is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of DAC38RFxx. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 terminal interface by SIF4_ENA in register IO_CONFIG (8.5.2). In both configurations, SCLK is the serial interface input clock and SDEN is serial interface enable. For 3 terminal configuration, SDIO is a bidirectional terminal for both data in and data out. For 4 terminal configuration, SDIO is bidirectional and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

The SPI registers are reset by writing a 1 to SPI_RESET in register RESET_CONFIG (8.5.1).

Each read/write operation is framed by signal SDEN (Serial Data Enable Bar) asserted low. The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. Figure 58 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 59 shows the serial interface timing diagram for a DAC38RFxx write operation. SCLK is the serial interface clock input to DAC38RFxx. Serial data enable SDEN is an active low input to DAC38RFxx. SDIO is serial data input. Input data to DAC38RFxx is clocked on the rising edges of SCLK.

Figure 59. Serial Interface Write Timing Diagram

Figure 60 shows the serial interface timing diagram for a DAC38RFxx read operation. SCLK is the serial interface clock input to DAC38RFxx. Serial data enable SDEN\ is an active low input to DAC38RFxx. SDIO is serial data input during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC38RFxx during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, both SDIO and SDO are data out from the DAC38RFxx during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge of SDEN when they will 3-state.

Figure 60. Serial Interface Read Timing Diagram

n the SIF interface there are four types of registers:

Table 42. Register Summary

8.5.1 Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]

8.5.2 IO Configuration Register (address = 0x01) [reset = 0x1800]

8.5.3 Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]

8.5.4 Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF

8.5.5 SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]

8.5.6 SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]

8.5.7 Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]

8.5.8 Page Set Register (address = 0x09) [reset = 0x0000]

8.5.9 SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]

8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]

8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]

8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0008]]

8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]

8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]

8.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300]

8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]

8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]

8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]

8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]