ZHCSQK5 May 2022 DAC53001 , DAC53002 , DAC63001 , DAC63002
PRODUCTION DATA
PMBus page address = FFh, PMBus register address = E8h
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GF-EN | X | GPO-EN | GPO-CONFIG | GPI-CH-SEL | GPI-CONFIG | GPI-EN | |||||||||
| R/W-0h | X-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | GF-EN | R/W | 0 | 0: Glitch filter disabled for
GP input. This setting provides faster response. 1: Glitch filter enabled for GPI. This setting introduces additional propagation delay but provides robustness. |
| 14 | X | X | 0 | Don't care. |
| 13 | GPO-EN | R/W | 0 | 0: Disable output mode for
GPIO pin. 1: Enable output mode for GPIO pin. |
| 12-9 | GPO-CONFIG | R/W | 0000 | STATUS function setting. The GPIO
pin is mapped to the following register bits as output: 0001: NVM-BUSY 0100: DAC-1-BUSY 0111: DAC-0-BUSY 1000: WIN-CMP-1 1011:WIN-CMP-0 Others: NA |
| 8-5 | GPI-CH-SEL | R/W | 0000 | Two bits correspond to two DAC channels. 0b is
disabled and 1b is enabled. GPI-CH-SEL[0]: Channel 1 GPI-CH-SEL[3]: Channel 0Example: when GPI-CH-SEL is 1001, both channel-0 and channel-1 are enabled. |
| 4-1 | GPI-CONFIG | R/W | 0000 | GPIO pin input configuration. Global settings act on the entire device. Channel-specific settings are dependent on the channel selection by the GPI-CH-SEL bits:0000: DEEP-SLEEP (global). GPIO falling edge triggers deep-sleep mode, GPIO rising edge brings the device out of deep-sleep.0010: FAULT-DUMP (global). GPIO falling edge triggers fault dump, GPIO = 1 has no effect.0011: IOUT power up-down (channel-specific). GPIO falling edge triggers power down, GPIO rising edge triggers power up.0100: VOUT power up-down (channel-specific). The output load is as per the VOUT-PDN-X setting. GPIO falling edge triggers power down, GPIO rising edge triggers power up.0101: PROTECT input (global). GPIO falling edge asserts PROTECT function, GPIO = 1 has no effect.0111: CLR input (global). GPIO = 0 asserts CLR function, GPIO = 1 has no effect.1000: LDAC input (channel-specific). GPIO falling edge asserts LDAC function, GPIO = 1 has no effect. Both the SYNC-CONFIG-X and the GPI-CH-SEL must be configured for every channel.1001: Start and stop function generation (channel-specific). GPIO falling edge stops function generation. GPIO rising edge starts function generation.1010: Trigger margin high-low (channel-specific). GPIO falling edge triggers margin low. GPIO rising edge triggers margin high.1011: RESET input (global). The falling edge of the GPIO pin asserts the RESET function. The RESET input must be a pulse. The GPIO rising edge brings the device out of reset. The RESET configuration must be programmed into the NVM. Otherwise the setting is cleared after the device reset. 1100: NVM write protection (global). GPIO falling edge allows NVM programming. GPIO rising edge blocks NVM programming.1101: Register-map lock (global). GPIO falling edge allows update to the register map. GPIO rising edge blocks any register map update except a write to the DEV-UNLOCK field through I2C or SPI and to the RESET field through I2C.Others: Invalid |
| 0 | GPI-EN | R/W | 0 | 0: Disable input mode for
GPIO pin. 1: Enable input mode for GPIO pin. |