ZHCSQK5 May   2022 DAC53001 , DAC53002 , DAC63001 , DAC63002

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
      4. 7.3.4 Power Consumption
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
        1. 7.4.3.1 Programmable Hysteresis Comparator
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 Fault-Dump Mode
      5. 7.4.5 Application-Specific Modes
        1. 7.4.5.1 Voltage Margining and Scaling
          1. 7.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 Function Generation
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 Device Reset and Fault Management
        1. 7.4.6.1 Power-On Reset (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 7.4.7 Power-Down Mode
        1. 7.4.7.1 Deep-Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      20. 7.6.20 PMBUS-PAGE Register [reset = 0300h]
      21. 7.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
      22. 7.6.22 PMBUS-CML Register [reset = 0000h]
      23. 7.6.23 PMBUS-VERSION Register [reset = 2200h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.4.5.1.2 Programmable Slew-Rate Control

When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new code following the slew rate and settling time specified in the Electrical Characteristics.

The slew rate control feature allows the user to control the rate at which the output voltage (VOUT) changes. When this feature is enabled (using the SLEW-RATE-X[3:0] bits), the DAC output changes from the current code to the code in the DAC-X-MARGIN-HIGH or DAC-X-MARGIN-LOW registers (when margin high or low commands are issued to the DAC) using the step size and time-period per step set in CODE-STEP-X and SLEW-RATE-X bits in the DAC-X-FUNC-CONFIG register:

  • SLEW-RATE-X defines the time-period per step at which the digital slew updates.
  • CODE-STEP-X defines the number of LSBs by which the output value changes at each update, for the corresponding channels.

Table 7-5 and Table 7-6 show different settings available for CODE-STEP-X and SLEW-RATE-X. With the default slew rate control setting of no-slew, the output changes immediately at a rate limited by the output drive circuitry and the attached load.

When the slew rate control feature is used, the output changes happen at the programmed slew rate. Figure 7-10 shows that this configuration results in a staircase formation at the output. Do not write to CODE-STEP-X, SLEW-RATE-X, or DAC-X-DATA during the output slew operation. Equation 6 provides the equation for the calculating the slew time (tSLEW).

Figure 7-10 Programmable Slew-Rate Control
Equation 6. tSLEW=SLEW_RATE×MARGIN_HIGH-MARGIN_LOW+1CODE_STEP

where:

  • SLEW_RATE is the SLEW-RATE-X setting specified in Table 7-6.
  • CODE_STEP is the CODE-STEP-X setting specified in Table 7-5.
  • MARGIN_HIGH is the DAC-X-MAGIN-HIGH specified in Section 7.6.2.
  • MARGIN_LOW is the DAC-X-MAGIN-LOW specified in Section 7.6.3.
Table 7-5 Code Step
REGISTER CODE-STEP-X[2] CODE-STEP-X[1] CODE-STEP-X[0] CODE STEP SIZE
DAC-X-FUNC-CONFIG 0 0 0 1 LSB (default)
0 0 1 2 LSB
0 1 0 3 LSB
0 1 1 4 LSB
1 0 0 6 LSB
1 0 1 8 LSB
1 1 0 16 LSB
1 1 1 32 LSB
Table 7-6 Slew Rate
REGISTER SLEW-RATE-X[3] SLEW-RATE-X[2] SLEW-RATE-X[1] SLEW-RATE-X[0] TIME PERIOD
(PER STEP)
DAC-X-FUNC-CONFIG 0 0 0 0 No slew (default)
0 0 0 1 4 µs
0 0 1 0 8 µs
0 0 1 1 12 µs
0 1 0 0 18 µs
0 1 0 1 27 µs
0 1 1 0 40.5 µs
0 1 1 1 60.75 µs
1 0 0 0 91.13 µs
1 0 0 1 136.69 µs
1 0 1 0 239.2 µs
1 0 1 1 418.61 µs
1 1 0 0 732.56 µs
1 1 0 1 1281.98 µs
1 1 1 0 2563.96 µs
1 1 1 1 5127.92 µs
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