ZHCSQK5 May   2022 DAC53001 , DAC53002 , DAC63001 , DAC63002

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
      4. 7.3.4 Power Consumption
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
        1. 7.4.3.1 Programmable Hysteresis Comparator
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 Fault-Dump Mode
      5. 7.4.5 Application-Specific Modes
        1. 7.4.5.1 Voltage Margining and Scaling
          1. 7.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 Function Generation
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 Device Reset and Fault Management
        1. 7.4.6.1 Power-On Reset (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 7.4.7 Power-Down Mode
        1. 7.4.7.1 Deep-Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      20. 7.6.20 PMBUS-PAGE Register [reset = 0300h]
      21. 7.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
      22. 7.6.22 PMBUS-CML Register [reset = 0000h]
      23. 7.6.23 PMBUS-VERSION Register [reset = 2200h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics: Voltage Output

at 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), digital inputs at VDD or AGND, all minimum and maximum specifications at –40°C ≤ TA ≤ +125°C, and typical specifications at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC63002, DAC63001 12 Bits
DAC53002, DAC53001 10
INL Integral nonlinearity(1) DAC63002, DAC63001 –4 4 LSB
DAC53002, DAC53001 –1 1
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error(4) Code 0d into DAC, external reference, VDD = 5.5 V 6 12 mV
Code 0d into DAC, internal VREF, gain = 4x, VDD = 5.5 V 6 15
Zero-code error temperature coefficient(4) Code 0d into DAC ±10 µV/°C
Offset error(4) (6) 1.7 V ≤ VDD < 2.7 V, FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution		 –0.75 0.3 0.75 %FSR
2.7 V ≤ VDD ≤ 5.5 V, FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution		 –0.5 0.25 0.5
Offset-error temperature coefficient(4) FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution		 ±0.0003 %FSR/°C
Gain error(4) Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution –0.5 0.25 0.5 %FSR
Gain-error temperature coefficient(4) Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution ±0.0008 %FSR/°C
Full-scale error(4) (6) 1.7 V ≤ VDD < 2.7 V, DAC at full-scale –1 1 %FSR
2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale –0.5 0.5
Full-scale-error temperature coefficient(4) DAC at full-scale ±0.0008 %FSR/°C
OUTPUT
Output voltage Reference tied to VDD 0 VDD V
CL Capacitive load(2) RL = infinite, phase margin = 30° 200 pF
Phase margin = 30° 1000
Short-circuit current VDD = 1.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 15 mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 50
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 60
Output-voltage headroom(2) To VDD (DAC output unloaded, internal reference = 1.21 V), 
VDD ≥ 1.21 V ☓ gain + 0.2 V		 0.2 V
To VDD and AGND (DAC output unloaded, external reference at VDD, gain = 1x, the VREF pin is not shorted to VDD) 0.8 %FSR
To VDD and AGND (ILOAD = 10 mA at VDD = 5.5 V,
ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), external reference at VDD, gain = 1x, the VREF pin is not shorted to VDD		 10
ZO VFB dc output impedance(3) DAC output enabled, internal reference (gain = 1.5x or 2x) or external reference at VDD (gain = 1x), the VREF pin is not shorted to VDD 400 500 600 kΩ
DAC output enabled, internal VREF, gain = 3x or 4x 325 400 485
Power supply rejection ratio (dc) Internal VREF, gain = 2x, DAC at midscale, VDD = 5 V ±10% 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR,
VDD = 5.5 V		 20 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR,
VDD = 5.5 V, internal VREF, gain = 4x		 25
Slew rate VDD = 5.5 V 0.3 V/µs
Power-on glitch magnitude At startup (DAC output disabled) 75 mV
At startup (DAC output disabled), RL = 100 kΩ 200
Output-enable glitch magnitude DAC output disabled to enabled (DAC registers at zero scale), RL = 100 kΩ 250 mV
Vn Output noise voltage (peak to peak) f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 50 µVPP
Internal VREF, gain = 4x, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V		 90
Output noise density f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.35 µV/√Hz
Internal VREF, gain = 4x, f = 1 kHz, DAC at midscale,
VDD = 5.5 V		 0.9
Power supply rejection ratio (ac)(3) Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale -68 dB
Code change glitch impulse ±1-LSB change around midscale (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1-LSB change around midscale (including feedthrough) 15 mV
POWER
IDD Current flowing into VDD(4) (5) Normal operation, DACs at full scale, digital pins static, external reference at VDD but the VREF pin is not shorted to VDD 35 50 µA/ch
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4) Measured with DAC output unloaded.
(5) The total power consumption is calculated by IDD x (total number of channels powered on) + (sleep-mode current).
(6) When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show parametric drift.
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