The DACx3004W are quad-channel buffered, force-sense output, voltage-output and current-output smart DACs that include an NVM and internal reference, and are available in a tiny 1.75-mm × 1.75-mm DSBGA package. The external reference must not exceed V_DD, either during transient or steady-state conditions. For the best Hi-Z output performance, use a pullup resistor on the VREF pin to VDD. In case the VDD pin remains floating during the off condition, place a 100-kΩ resistor to AGND for proper detection of the VDD pin off condition. All the digital outputs are open drain; use external pullup resistors on these pins. The interface protocol is detected at power-on, and the device locks to the protocol as long as V_DD is on. In I²C mode, when allocating the I²C addresses in the system, also consider the broadcast address. I²C timeout can be enabled for robustness. SPI mode is three-wire by default. Configure the GPIO pin as SDO in the NVM for SPI readback capability. The SPI clock speed in readback mode is slower than in write mode. Power-down mode sets the DAC outputs in Hi-Z by default. Change the configuration appropriately for different power-down settings. The DAC channels can also power-up with a programmed DAC code in the NVM.