The DACx3202 devices consist of a string architecture with a voltage-output amplifier, as well as an external FB pin and voltage-to-current converter for each channel. Section 7.2 shows the DAC architecture within the block diagram that operates from a 1.8-V to 5.5-V power supply. The DAC has an internal voltage reference of 1.21 V. Optionally, use an external reference on the VREF pin, or use the power supply as a reference. Voltage output mode uses one of these three reference options. Current output mode uses an internal band gap to generate the current outputs. Both the voltage- and current-output modes support multiple programmable output ranges.

The DACx3202 devices support Hi-Z output when VDD is off, maintaining very low leakage current at the output pins with up to 1.25 V of forced voltage. The DAC output pin also starts up in high-impedance mode by default, making these devices an excellent choice for voltage margining and scaling applications. To change the power-up mode to 10 kΩ-GND or 100 kΩ-GND, program the corresponding VOUT-PDN-X field in the COMMON-CONFIG register and load these bits in the device NVM.

The DACx3202 devices support an independent comparator mode for each channel. The respective FBx pin acts as an input for the comparator. The DAC architecture supports inversion of the comparator output using register settings. The comparator outputs can be push-pull or open-drain. The comparator mode supports programmable hysteresis using the margin-high and margin-low register fields, latching comparator, and window comparator. The comparator outputs are accessible internally by the device.

The DACx3202 devices include a smart feature set to enable processor-less operation and high integration. The NVM enables a predictable start-up. In the absence of a processor or when the processor or software fails, the GPIO triggers the DAC output without the I²C interface. The integrated functions and the FBx pin enable PWM output for control applications. The FBx pin enables this device to be used as a programmable comparator. The digital slew-rate control and the Hi-Z power-down modes enable a hassle-free voltage margining and scaling function.