The DACx3202 family of devices includes a power-on reset (POR) function that controls the output voltage at power up. After the V_DD supply has been established, a POR event is issued. The POR causes all registers to initialize to default values, and communication with the device is valid only after a POR (boot-up) delay. The default value for all the registers in the DACx3202 is loaded from NVM as soon as the POR event is issued.

When the device powers up, a POR circuit sets the device to the default mode. Figure 7-13 indicates that the POR circuit requires specific V_DD levels to make sure that the internal capacitors discharge and reset the device at power up. To make sure that a POR occurs, V_DD must be less than 0.7 V for at least 1 ms. When V_DD drops to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When V_DD remains greater than 1.65 V, a POR does not occur.

Figure 7-13 Threshold Levels for V_DD POR Circuit