ZHCSQC6 May 2022 DAC53202 , DAC63202
PRODUCTION DATA
An SPI access cycle for DACx3202 is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a continuous or gated clock. SDI data are clocked on SCLK falling edges. The SPI frame for DACx3202 is 24 bits long. Therefore, the SYNC pin must stay low for at least 24 SCLK falling edges. The access cycle ends when the SYNC pin is deasserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored. By default, the SDO pin is not enabled (three-wire SPI). In the three-wire SPI mode, if the access cycle contains more than the minimum clock edges, only the first 24 bits are used by the device. When SYNC is high, the SCLK and SDI signals are blocked, and SDO becomes Hi-Z to allow data readback from other devices connected on the bus.
Table 7-12 and Figure 7-14 describe the format for the 24-bit SPI access cycle. The first byte input to SDI is the instruction cycle. The instruction cycle identifies the request as a read or write command and the 7-bit address that is to be accessed. The last 16 bits in the cycle form the data cycle.
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 23 | R/W | Identifies the communication as a read or write command to the address register: R/W = 0 sets a write operation. R/W = 1 sets a read operation |
| 22-16 | A[6:0] | Register address: specifies the register to be accessed during the read or write operation |
| 15-0 | DI[15:0] | Data cycle bits: If a write command, the data cycle bits are the values to be written to the register with address A[6:0]. If a read command, the data cycle bits are don't care values. |
Read operations require that the SDO pin is first enabled by setting the SDO-EN bit in the INTERFACE-CONFIG register. This configuration is called four-wire SPI. A read operation is initiated by issuing a read command access cycle. After the read command, a second access cycle must be issued to get the requested data. Table 7-13 and Figure 7-15 show the output data format. Data are clocked out on the SDO pin either on the falling edge or rising edge of SCLK according to the FSDO bit (see also Figure 6-3).
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 23 | R/W | Echo R/W from previous access cycle |
| 22-16 | A[6:0] | Echo register address from previous access cycle |
| 15-0 | DI[15:0] | Readback data requested on previous access cycle |
The daisy-chain operation is also enabled with the SDO pin. Figure 7-16 shows that in daisy-chain mode, multiple devices are connected in a chain with the SDO pin of one device is connected to SDI pin of the following device. The SPI host drives the SDI pin of the first device in the chain. The SDO pin of the last device in the chain is connected to the POCI pin of the SPI host. In four-wire SPI mode, if the access cycle contains multiples of 24 clock edges, only the last 24 bits are used by the device first device in the chain. If the access cycle contains clock edges that are not in multiples of 24, the SPI packet is ignored by the device. Figure 7-17 describes the packet format for the daisy-chain write cycle.