米6体育平台手机版

ZHCSOM0 October 2020 DAC43401-Q1 , DAC53401-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DSG|8
- MPDS308C

散热焊盘机械数据 (封装 | 引脚)

DSG|8
- QFND141I

订购信息

7.11 Typical Characteristics

at T_A = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

Reference = V_DD

Figure 7-21 Integral Linearity Error
vs Supply Voltage

Reference = V_DD

Figure 7-23 Total Unadjusted Error
vs Supply Voltage

Reference = V_DD

Figure 7-25 Offset Error vs Supply Voltage

Reference = V_DD

Figure 7-27 Full-Scale Error vs Supply Voltage

V_DD = 5.5 V

Figure 7-29 Supply Current vs Digital Input Code

Internal reference (gain = 4x), DAC at midscale

Figure 7-31 Supply Current vs Temperature

Reference = V_DD, DAC powered down

Figure 7-33 Power-Down Current vs Temperature

Reference = V_DD = 5.5 V, DAC code transition from midscale to midscale + 1 LSB, DAC load = 5kΩ || 200pF

Figure 7-35 Glitch Impulse, Rising Edge,
1-LSB Step

Reference = V_DD = 5.5 V, DAC load = 5kΩ || 200pF

Figure 7-37 Full-Scale Settling Time, Rising Edge

Reference = V_DD = 5.5 V

Figure 7-39 Power-on Glitch

Reference = V_DD = 5.5 V, Fast+ mode, DAC at midscale, DAC load = 5kΩ || 200pF

Figure 7-41 Clock Feedthrough

Reference = V_DD = 5.5 V

Figure 7-43 DAC Output Noise Spectral Density

Reference = V_DD = 5.5 V, DAC at midscale

Figure 7-45 DAC Output Noise: 0.1 Hz to 10 Hz

Reference = V_DD

Figure 7-22 Differential Linearity Error
vs Supply Voltage

Reference = V_DD

Figure 7-24 Zero-Code Error
vs Supply Voltage

Reference = V_DD

Figure 7-26 Gain Error vs Supply Voltage

V_DD = 1.8 V

Figure 7-28 Supply Current vs Digital Input Code

Reference = V_DD, DAC at midscale

Figure 7-30 Supply Current vs Temperature

DAC at midscale

Figure 7-32 Supply Current vs Supply Voltage

Figure 7-34 Source and Sink Capability

Reference = V_DD = 5.5 V, DAC code transition from midscale to midscale – 1 LSB, DAC load = 5kΩ || 200pF

Figure 7-36 Glitch Impulse, Falling Edge,
1-LSB Step

Reference = V_DD = 5.5 V, DAC load = 5kΩ || 200pF

Figure 7-38 Full-Scale Settling Time, Falling Edge

Reference = V_DD = 5.5 V

Figure 7-40 Power-off Glitch

Internal reference (gain = 4x), V_DD = 5.25 V + 0.25 V_PP, DAC at midscale, DAC load = 5kΩ || 200pF

Figure 7-42 DAC Output AC PSRR vs Frequency

Internal reference (gain = 4x), V_DD = 5.5 V

Figure 7-44 DAC Output Noise Spectral Density

Internal reference (gain = 4x), V_DD = 5.5 V, DAC at midscale

Figure 7-46 DAC Output Noise: 0.1 Hz to 10 Hz