The DACx3401-Q1 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown in the pin diagram of Section 6. The I²C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C-compatible devices connect to the I²C bus through the open drain I/O pins, SDA and SCL.

The I²C specification states that the device that controls communication is called a master, and the devices that are controlled by the master are called slaves. The master device generates the SCL signal. The master device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device on an I²C bus is typically a microcontroller or digital signal processor (DSP). The DACx3401-Q1 family operates as a slave device on the I²C bus. A slave device acknowledges master commands, and upon master control, receives or transmits data.

Typically, theDACx3401-Q1 family operates as a slave receiver. A master device writes to the DACx3401-Q1, a slave receiver. However, if a master device requires the DACx3401-Q1 internal register data, the DACx3401-Q1 operate as a slave transmitter. In this case, the master device reads from the DACx3401-Q1. According to I²C terminology, read and write refer to the master device.

The DACx3401-Q1 family is a slave and supports the following data transfer modes:

• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1.0 Mbps)

The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes. The DACx3401-Q1 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports the general call reset function. Sending the following sequence initiates a software reset within the device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the ACK bit, following the second byte.

Other than specific timing signals, the I²C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of the ninth clock cycle, as shown in Figure 8-3.

Figure 8-3 Acknowledge and Not Acknowledge on the I²C Bus