8.5.2 DACx3401 I²C Update Sequence

For a single update, the DACx3401 require a start condition, a valid I²C address byte, a command byte, and two data bytes, as listed in Table 10.

After each byte is received, the DACx3401 family acknowledges the byte by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 53. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I²C address byte selects the DACx3401 devices.

Figure 53. I²C Bus Protocol

The command byte sets the operating mode of the selected DACx3401 device. For a data update to occur when the operating mode is selected by this byte, the DACx3401 device must receive two data bytes: the most significant data byte (MSDB) and least significant data byte (LSDB). The DACx3401 device performs an update on the falling edge of the acknowledge signal that follows the LSDB.

When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using the fast+ mode (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received, the DACx3401 device releases the I²C bus and awaits a new start condition.