The DACx3508 supports a three-wire SPI with write-only functionality. An SPI write cycle for DACx3508 is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a continuous or gated clock. SDI data are clocked on SCLK falling edges. The SPI frame for DACx3508 is 24 bits long; therefore, the SYNC pin must stay low for at least 24 SCLK falling edges. The write cycle ends when the SYNC pin is deasserted high. If the write cycle contains less than the minimum clock edges, the communication is ignored. If the write cycle contains more than the minimum clock edges, only the first 24 bits are used by the device.

Table 6-1 describes the format for the 24-bit SPI write access cycle. The first byte input to SDI is the instruction cycle. The instruction cycle identifies the request as the 8-bit address to be written. The last 16 bits in the cycle form the data cycle.