The device stores the data written to the DAC data registers in the DAC buffer registers. Transfer of data from the DAC buffer registers to the DAC active registers can be set to happen immediately (asynchronous mode) or initiated by an LDAC trigger (synchronous mode). After the DAC active registers are updated, the DAC outputs change to the new values.

The update mode for each DAC channel is determined by the status of LDAC pin.

In asynchronous mode (LDAC = low before the DAC write command), a write to the DAC data register results in an immediate update of the DAC active register and DAC output at the 24th rising-edge of the clock.

In synchronous mode (LDAC = high before the DAC write command), writing to the DAC data register does not automatically update the DAC output. Instead, the update occurs only after LDAC is pulled low. The synchronous update mode enables simultaneous update of all DAC outputs.