米6体育平台手机版_好二三四

ZHCSM85A October 2020 – September 2023 DAC43701-Q1 , DAC53701-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DSG|8
- MPDS308C

散热焊盘机械数据 (封装 | 引脚)

DSG|8
- QFND141I

订购信息

zhcsm85a_oa

6.13 Typical Characteristics

at T_A = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

Reference = V_DD

Figure 6-22 Integral Linearity Error vs Supply Voltage

Reference = V_DD

Figure 6-24 Total Unadjusted Error vs Supply Voltage

Reference = V_DD

Figure 6-26 Offset Error vs Supply Voltage

Reference = V_DD

Figure 6-28 Full-Scale Error vs Supply Voltage

V_DD = 5.5 V

Figure 6-30 Supply Current vs Digital Input Code

Internal reference (gain = 4 ×), DAC at midscale

Figure 6-32 Supply Current vs Temperature

Reference = V_DD, DAC powered down

Figure 6-34 Power-Down Current vs Temperature

Reference = V_DD = 5.5 V, DAC code transition from midscale to midscale + 1 LSB, DAC load = 5 kΩ || 200 pF

Figure 6-36 Glitch Impulse, Rising Edge, 1-LSB Step

Reference = V_DD = 5.5 V, DAC load = 5 kΩ || 200 pF

Figure 6-38 Full-Scale Settling Time, Rising Edge

Reference = V_DD = 5.5 V

Figure 6-40 Power-on Glitch

Reference = V_DD = 5.5 V, fast-mode plus, DAC at midscale, DAC load = 5 kΩ || 200 pF

Figure 6-42 Clock Feedthrough

Reference = V_DD = 5.5 V

Figure 6-44 DAC Output Noise Spectral Density

Reference = V_DD = 5.5 V, DAC at midscale

Figure 6-46 DAC Output Noise: 0.1 Hz to 10 Hz

Reference = V_DD

Figure 6-23 Differential Linearity Error vs Supply Voltage

Reference = V_DD

Figure 6-25 Zero-Code Error vs Supply Voltage

Reference = V_DD

Figure 6-27 Gain Error vs Supply Voltage

V_DD = 1.8 V

Figure 6-29 Supply Current vs Digital Input Code

Reference = V_DD, DAC at midscale

Figure 6-31 Supply Current vs Temperature

DAC at midscale

Figure 6-33 Supply Current vs Supply Voltage

Figure 6-35 Source and Sink Capability

Reference = V_DD = 5.5 V, DAC code transition from midscale to midscale – 1 LSB, DAC load = 5 kΩ || 200 pF

Figure 6-37 Glitch Impulse, Falling Edge, 1-LSB Step

Reference = V_DD = 5.5 V, DAC load = 5 kΩ || 200 pF

Figure 6-39 Full-Scale Settling Time, Falling Edge

Reference = V_DD = 5.5 V

Figure 6-41 Power-off Glitch

Internal reference (gain = 4 ×), V_DD = 5.25 V + 0.25 V_PP, DAC at midscale, DAC load = 5 kΩ || 200 pF

Figure 6-43 DAC Output AC PSRR vs Frequency

Internal reference (gain = 4 ×), V_DD = 5.5 V

Figure 6-45 DAC Output Noise Spectral Density

Internal reference (gain = 4 ×), V_DD = 5.5 V, DAC at midscale

Figure 6-47 DAC Output Noise: 0.1 Hz to 10 Hz

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