The DAC539G2-Q1 uses a string architecture with a voltage-output amplifier for digital-to-analog converter functions. With an external FB pin, channel 0 functions as a programmable comparator. Channel 0 also functions as a voltage-to-PWM converter using a triangle or sawtooth waveform on the noninverting input of the amplifier. Channel 1 functions as a GPI-to-voltage converter using a look-up table with eight entries corresponding to all the binary combinations of the three GPI pins.

Section 7.2 shows the DAC architecture within the block diagram, which operates from a 1.8-V to 5.5-V power supply. Voltage output mode uses one of the three reference options: the power supply, the DAC internal voltage reference of 1.21 V, or an external reference. This device supports multiple programmable output ranges.

The DAC539G2-Q1 provides a state machine with configurable parameters, which converts three GPI signals to PWM output. Figure 7-1 shows the digital architecture of DAC539G2-Q1. The state machine is implemented in one-time programmable (OTP) memory that is one-to-one mapped to a static random access memory (SRAM). The application configuration data are stored in the SRAM section mapped to the NVM (EEPROM). The state machine can access the digital I/O directly while accessing the DAC outputs through the register map. The state machine is inaccessible by the end user. The state machine can be operated in standalone mode without interfacing to a processor (processor-less operation).

Figure 7-1 Smart DAC Architecture