ZHCSRN7A
January 2023 – September 2023
DAC539G2-Q1
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: Voltage Output
6.6
Electrical Characteristics: Comparator Mode
6.7
Electrical Characteristics: General
6.8
Timing Requirements: I2C Standard Mode
6.9
Timing Requirements: I2C Fast Mode
6.10
Timing Requirements: I2C Fast Mode Plus
6.11
Timing Requirements: SPI Write Operation
6.12
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
6.13
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
6.14
Timing Requirements: GPIO
6.15
时序图
6.16
典型特性:电压输出
6.17
Typical Characteristics: Comparator
6.18
典型特性:通用
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Smart Digital-to-Analog Converter (DAC) Architecture
7.3.2
Programming Interface
7.3.3
Nonvolatile Memory (NVM)
7.4
Device Functional Modes
7.4.1
GPI-to-Voltage Converter
7.4.1.1
Voltage Reference and DAC Transfer Function
7.4.1.2
Power-Supply as Reference
7.4.1.3
Internal Reference
7.4.1.4
External Reference
7.4.2
Voltage-to-PWM Converter
7.4.2.1
Function Generation
7.4.2.1.1
Triangular Waveform Generation
7.4.2.1.2
Sawtooth Waveform Generation
7.4.2.1.3
PWM Frequency Correction
7.4.3
Device Reset and Fault Management
7.4.3.1
Power-On Reset (POR)
7.4.3.2
External Reset
7.4.3.3
Register-Map Lock
7.4.3.4
NVM Cyclic Redundancy Check (CRC)
7.4.3.4.1
NVM-CRC-FAIL-USER Bit
7.4.3.4.2
NVM-CRC-FAIL-INT Bit
7.4.4
Power-Down Mode
7.5
Programming
7.5.1
SPI Programming Mode
7.5.2
I2C Programming Mode
7.5.2.1
F/S Mode Protocol
7.5.2.2
I2C Update Sequence
7.5.2.2.1
Address Byte
7.5.2.2.2
Command Byte
7.5.2.3
I2C Read Sequence
7.6
Register Maps
7.6.1
NOP Register (address = 00h) [reset = 0000h]
7.6.2
DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
7.6.3
COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
7.6.4
COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
7.6.5
FUNCTION-TRIGGER Register (address = 21h) [reset = 0001h]
7.6.6
GENERAL-STATUS Register (address = 22h) [reset = 2068h]
7.6.7
DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
7.6.8
INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
7.6.9
STATE-MACHINE-CONFIG Register (address = 27h) [reset = 0003h]
7.6.10
SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
7.6.11
SRAM-DATA Register (address = 2Ch) [reset = 0000h]
7.6.12
FUNCTION-CONFIG Register (SRAM address = 20h) [reset = 007Ah]
7.6.13
FUNCTION-MAX Register (SRAM address = 21h) [reset = B900h]
7.6.14
FUNCTION-MIN Register (SRAM address = 22h) [reset = 1900h]
7.6.15
GPI-DEBOUNCE Register (SRAM address = 23h) [reset = 0138h]
7.6.16
VOUT-DATA-X Register (SRAM address = 24h to 2Bh) [reset = see #GUID-D64978E3-E8F0-4408-A2C1-8C72D24777EC/X6961 ]
7.6.17
PWM-FREQUENCY-ERROR Register (SRAM address = 9Eh) [reset = device-specific]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.2
接收文档更新通知
9.3
支持资源
9.4
Trademarks
9.5
静电放电警告
9.6
术语表
10
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
RTE|16
MPQF149D
散热焊盘机械数据 (封装 | 引脚)
RTE|16
QFND525B
订购信息
zhcsrn7a_oa
zhcsrn7a_pm
8.4
Layout
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