ZHCSRN7A January 2023 – September 2023 DAC539G2-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: Voltage Output
- 6.6 Electrical Characteristics: Comparator Mode
- 6.7 Electrical Characteristics: General
- 6.8 Timing Requirements: I2C Standard Mode
- 6.9 Timing Requirements: I2C Fast Mode
- 6.10 Timing Requirements: I2C Fast Mode Plus
- 6.11 Timing Requirements: SPI Write Operation
- 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
- 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
- 6.14 Timing Requirements: GPIO
- 6.15 时序图
- 6.16 典型特性：电压输出
- 6.17 Typical Characteristics: Comparator
- 6.18 典型特性：通用
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 NOP Register (address = 00h) [reset = 0000h]
- 7.6.2 DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
- 7.6.3 COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
- 7.6.4 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
- 7.6.5 FUNCTION-TRIGGER Register (address = 21h) [reset = 0001h]
- 7.6.6 GENERAL-STATUS Register (address = 22h) [reset = 2068h]
- 7.6.7 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
- 7.6.8 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
- 7.6.9 STATE-MACHINE-CONFIG Register (address = 27h) [reset = 0003h]
- 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
- 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
- 7.6.12 FUNCTION-CONFIG Register (SRAM address = 20h) [reset = 007Ah]
- 7.6.13 FUNCTION-MAX Register (SRAM address = 21h) [reset = B900h]
- 7.6.14 FUNCTION-MIN Register (SRAM address = 22h) [reset = 1900h]
- 7.6.15 GPI-DEBOUNCE Register (SRAM address = 23h) [reset = 0138h]
- 7.6.16 VOUT-DATA-X Register (SRAM address = 24h to 2Bh) [reset = see #GUID-D64978E3-E8F0-4408-A2C1-8C72D24777EC/X6961 ]
- 7.6.17 PWM-FREQUENCY-ERROR Register (SRAM address = 9Eh) [reset = device-specific]
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
6.16 典型特性：电压输出
TA = 25°C，VDD = 5.5V，外部基准 = 5.5V，增益 = 1 x 且 DAC 输出为空载（除非另有说明）
| 内部基准，增益 = 4 × |
| 内部基准，增益 = 4 × |
| 内部基准，增益 = 4 × |
| DAC 通道位于中标度 |
| DAC 通道位于中标度 |
| 零标度到满量程摆幅 |
| DAC 处于高阻态断电模式 |
| 内部基准，增益 = 4 × |
| 内部基准，增益 = 4x，f = 0.1Hz 至 10Hz |
| DAC 通道位于中标度 |
| 满量程到零标度摆幅 |
| DAC 处于零标度 |
| f = 0.1Hz 至 10Hz |