ZHCSRN7A January 2023 – September 2023 DAC539G2-Q1
PRODUCTION DATA
This design uses a dual-channel, buffered voltage output smart DAC to decode three GPIs into a constant-frequency PWM output with eight selectable duty-cycle levels. In this design, the integrated buffer acts as a comparator, and a triangle or sawtooth waveform generated by the device acts as the threshold for the comparator. The DAC539G2-Q1 output buffers have an exposed feedback path through the feedback pin (FBx), which acts as the voltage input to the comparator. The comparator generates a PWM output with the same frequency as the triangle or sawtooth wave, and a duty cycle that depends on the FBx input. Use this circuit in applications such as automotive rear lights, rear light fault indication, and fault communication in factory automation and control designs. Figure 8-1 shows how to connect the two DAC outputs to achieve a PWM output.