The DAC539G2-Q1 has a 2-wire serial interface (SCL and SDA), and one address pin (A0); see also Figure 5-1. The I²C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I²C-compatible devices connect to the I²C bus through the open drain I/O pins, SDA and SCL.

The I²C specification states that the device that controls communication is called a controller, and the devices that are controlled by the controller are called targets. The controller generates the SCL signal. The controller also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is completed by the controller. The controller on an I²C bus is typically a microcontroller or digital signal processor (DSP). The DAC539G2-Q1 operates as a target on the I²C bus. A target acknowledges controller commands, and upon controller control, receives or transmits data.

Typically, the DAC539G2-Q1 family operates as a target receiver. A controller writes to the DAC539G2-Q1, a target receiver. However, if a controller requires the DAC539G2-Q1 internal register data, the DAC539G2-Q1 operates as a target transmitter. In this case, the controller reads from the DAC539G2-Q1. According to I²C terminology, read and write refer to the controller.

The DAC539G2-Q1 supports the following data transfer modes:

• Standard mode (100Kbps)
• Fast mode (400Kbps)
• Fast mode plus (1.0Mbps)

The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but not output current. The low-level output current is 3 mA; similar to the case of standard and fast modes. The DAC539G2-Q1 supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports the general call reset function. Sending the following sequence initiates a software reset within the device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the ACK bit, following the second byte.

Other than specific timing signals, the I²C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. Figure 7-11 depicts a not-acknowledge, when the SDA line is left high during the high period of the ninth clock cycle.

Figure 7-11 Acknowledge and Not Acknowledge on the I²C Bus